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Searched refs:RIUBASE_IRQ (Results 1 – 16 of 16) sorted by relevance

/utopia/UTPA2-700.0.x/modules/irq/hal/mainz/irq/
H A DregIRQ.h109 #define RIUBASE_IRQ 0x1900 //(0x101900-0x100000) macro
112 #define REG_AEON_C_FIQ_MASK (RIUBASE_IRQ + (0x0064 << 1))
113 #define REG_AEON_C_FIQ_CLR (RIUBASE_IRQ + (0x006C << 1))
114 #define REG_AEON_FIQ_FINAL_STATUS (RIUBASE_IRQ + (0x006C << 1))
116 #define REG_AEON_C_IRQ_MASK (RIUBASE_IRQ + (0x0074 << 1))
117 #define REG_AEON_IRQ_FINAL_STATUS (RIUBASE_IRQ + (0x007C << 1))
126 #define REG_MIPS_C_FIQ_MASK (RIUBASE_IRQ + (0x0024 << 1))
127 #define REG_MIPS_C_FIQ_CLR (RIUBASE_IRQ + (0x002C << 1))
128 #define REG_MIPS_FIQ_FINAL_STATUS (RIUBASE_IRQ + (0x002C << 1))
130 #define REG_MIPS_C_IRQ_MASK (RIUBASE_IRQ + (0x0034 << 1))
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/utopia/UTPA2-700.0.x/modules/irq/hal/mooney/irq/
H A DregIRQ.h109 #define RIUBASE_IRQ 0x1900 //(0x101900-0x100000) macro
112 #define REG_AEON_C_FIQ_MASK (RIUBASE_IRQ + (0x0064 << 1))
113 #define REG_AEON_C_FIQ_CLR (RIUBASE_IRQ + (0x006C << 1))
114 #define REG_AEON_FIQ_FINAL_STATUS (RIUBASE_IRQ + (0x006C << 1))
116 #define REG_AEON_C_IRQ_MASK (RIUBASE_IRQ + (0x0074 << 1))
117 #define REG_AEON_IRQ_FINAL_STATUS (RIUBASE_IRQ + (0x007C << 1))
126 #define REG_MIPS_C_FIQ_MASK (RIUBASE_IRQ + (0x0024 << 1))
127 #define REG_MIPS_C_FIQ_CLR (RIUBASE_IRQ + (0x002C << 1))
128 #define REG_MIPS_FIQ_FINAL_STATUS (RIUBASE_IRQ + (0x002C << 1))
130 #define REG_MIPS_C_IRQ_MASK (RIUBASE_IRQ + (0x0034 << 1))
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/utopia/UTPA2-700.0.x/modules/irq/hal/messi/irq/
H A DregIRQ.h109 #define RIUBASE_IRQ 0x1900 //(0x101900-0x100000) macro
112 #define REG_AEON_C_FIQ_MASK (RIUBASE_IRQ + (0x0064 << 1))
113 #define REG_AEON_C_FIQ_CLR (RIUBASE_IRQ + (0x006C << 1))
114 #define REG_AEON_FIQ_FINAL_STATUS (RIUBASE_IRQ + (0x006C << 1))
116 #define REG_AEON_C_IRQ_MASK (RIUBASE_IRQ + (0x0074 << 1))
117 #define REG_AEON_IRQ_FINAL_STATUS (RIUBASE_IRQ + (0x007C << 1))
126 #define REG_MIPS_C_FIQ_MASK (RIUBASE_IRQ + (0x0024 << 1))
127 #define REG_MIPS_C_FIQ_CLR (RIUBASE_IRQ + (0x002C << 1))
128 #define REG_MIPS_FIQ_FINAL_STATUS (RIUBASE_IRQ + (0x002C << 1))
130 #define REG_MIPS_C_IRQ_MASK (RIUBASE_IRQ + (0x0034 << 1))
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/utopia/UTPA2-700.0.x/modules/irq/hal/kano/irq/
H A DregIRQ.h110 #define RIUBASE_IRQ 0x1900 //(0x101900-0x100000) macro
114 #define REG_AEON_C_FIQ_MASK (RIUBASE_IRQ + (0x24 << 1))
115 #define REG_AEON_C_FIQ_CLR (RIUBASE_IRQ + (0x2C << 1))
116 #define REG_AEON_FIQ_FINAL_STATUS (RIUBASE_IRQ + (0x2C << 1))
118 #define REG_AEON_C_IRQ_MASK (RIUBASE_IRQ + (0x34 << 1))
119 #define REG_AEON_IRQ_FINAL_STATUS (RIUBASE_IRQ + (0x3C << 1))
134 #define REG_MIPS_C_FIQ_MASK (RIUBASE_IRQ + (0x44 << 1))
135 #define REG_MIPS_C_FIQ_CLR (RIUBASE_IRQ + (0x4c << 1))
136 #define REG_MIPS_FIQ_FINAL_STATUS (RIUBASE_IRQ + (0x4c << 1))
138 #define REG_MIPS_C_IRQ_MASK (RIUBASE_IRQ + (0x54 << 1))
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/utopia/UTPA2-700.0.x/modules/irq/hal/k7u/irq/
H A DregIRQ.h110 #define RIUBASE_IRQ 0x1900 //(0x101900-0x100000) macro
114 #define REG_AEON_C_FIQ_MASK (RIUBASE_IRQ + (0x24 << 1))
115 #define REG_AEON_C_FIQ_CLR (RIUBASE_IRQ + (0x2C << 1))
116 #define REG_AEON_FIQ_FINAL_STATUS (RIUBASE_IRQ + (0x2C << 1))
118 #define REG_AEON_C_IRQ_MASK (RIUBASE_IRQ + (0x34 << 1))
119 #define REG_AEON_IRQ_FINAL_STATUS (RIUBASE_IRQ + (0x3C << 1))
134 #define REG_MIPS_C_FIQ_MASK (RIUBASE_IRQ + (0x44 << 1))
135 #define REG_MIPS_C_FIQ_CLR (RIUBASE_IRQ + (0x4c << 1))
136 #define REG_MIPS_FIQ_FINAL_STATUS (RIUBASE_IRQ + (0x4c << 1))
138 #define REG_MIPS_C_IRQ_MASK (RIUBASE_IRQ + (0x54 << 1))
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/utopia/UTPA2-700.0.x/modules/irq/hal/k6lite/irq/
H A DregIRQ.h110 #define RIUBASE_IRQ 0x1900 //(0x101900-0x100000) macro
114 #define REG_AEON_C_FIQ_MASK (RIUBASE_IRQ + (0x24 << 1))
115 #define REG_AEON_C_FIQ_CLR (RIUBASE_IRQ + (0x2C << 1))
116 #define REG_AEON_FIQ_FINAL_STATUS (RIUBASE_IRQ + (0x2C << 1))
118 #define REG_AEON_C_IRQ_MASK (RIUBASE_IRQ + (0x34 << 1))
119 #define REG_AEON_IRQ_FINAL_STATUS (RIUBASE_IRQ + (0x3C << 1))
134 #define REG_MIPS_C_FIQ_MASK (RIUBASE_IRQ + (0x44 << 1))
135 #define REG_MIPS_C_FIQ_CLR (RIUBASE_IRQ + (0x4c << 1))
136 #define REG_MIPS_FIQ_FINAL_STATUS (RIUBASE_IRQ + (0x4c << 1))
138 #define REG_MIPS_C_IRQ_MASK (RIUBASE_IRQ + (0x54 << 1))
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/utopia/UTPA2-700.0.x/modules/irq/hal/curry/irq/
H A DregIRQ.h110 #define RIUBASE_IRQ 0x1900 //(0x101900-0x100000) macro
114 #define REG_AEON_C_FIQ_MASK (RIUBASE_IRQ + (0x24 << 1))
115 #define REG_AEON_C_FIQ_CLR (RIUBASE_IRQ + (0x2C << 1))
116 #define REG_AEON_FIQ_FINAL_STATUS (RIUBASE_IRQ + (0x2C << 1))
118 #define REG_AEON_C_IRQ_MASK (RIUBASE_IRQ + (0x34 << 1))
119 #define REG_AEON_IRQ_FINAL_STATUS (RIUBASE_IRQ + (0x3C << 1))
134 #define REG_MIPS_C_FIQ_MASK (RIUBASE_IRQ + (0x44 << 1))
135 #define REG_MIPS_C_FIQ_CLR (RIUBASE_IRQ + (0x4c << 1))
136 #define REG_MIPS_FIQ_FINAL_STATUS (RIUBASE_IRQ + (0x4c << 1))
138 #define REG_MIPS_C_IRQ_MASK (RIUBASE_IRQ + (0x54 << 1))
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/utopia/UTPA2-700.0.x/modules/irq/hal/k6/irq/
H A DregIRQ.h110 #define RIUBASE_IRQ 0x1900 //(0x101900-0x100000) macro
114 #define REG_AEON_C_FIQ_MASK (RIUBASE_IRQ + (0x24 << 1))
115 #define REG_AEON_C_FIQ_CLR (RIUBASE_IRQ + (0x2C << 1))
116 #define REG_AEON_FIQ_FINAL_STATUS (RIUBASE_IRQ + (0x2C << 1))
118 #define REG_AEON_C_IRQ_MASK (RIUBASE_IRQ + (0x34 << 1))
119 #define REG_AEON_IRQ_FINAL_STATUS (RIUBASE_IRQ + (0x3C << 1))
134 #define REG_MIPS_C_FIQ_MASK (RIUBASE_IRQ + (0x44 << 1))
135 #define REG_MIPS_C_FIQ_CLR (RIUBASE_IRQ + (0x4c << 1))
136 #define REG_MIPS_FIQ_FINAL_STATUS (RIUBASE_IRQ + (0x4c << 1))
138 #define REG_MIPS_C_IRQ_MASK (RIUBASE_IRQ + (0x54 << 1))
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/utopia/UTPA2-700.0.x/modules/irq/hal/mustang/irq/
H A DregIRQ.h107 #define RIUBASE_IRQ 0x1900 //(0x101900-0x100000) macro
116 #define REG_AEON_C_FIQ_MASK (RIUBASE_IRQ + (0x24*2))
117 #define REG_AEON_C_FIQ_CLR (RIUBASE_IRQ + (0x2C*2))
118 #define REG_AEON_FIQ_FINAL_STATUS (RIUBASE_IRQ + (0x2C*2))
120 #define REG_AEON_C_IRQ_MASK (RIUBASE_IRQ + (0x34*2))
121 #define REG_AEON_IRQ_FINAL_STATUS (RIUBASE_IRQ + (0x3C*2))
136 #define REG_MIPS_C_FIQ_MASK (RIUBASE_IRQ + 0x44*2)
137 #define REG_MIPS_C_FIQ_CLR (RIUBASE_IRQ + 0x4C*2)
138 #define REG_MIPS_FIQ_FINAL_STATUS (RIUBASE_IRQ + 0x4C*2)
140 #define REG_MIPS_C_IRQ_MASK (RIUBASE_IRQ + 0x54*2)
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/utopia/UTPA2-700.0.x/modules/irq/hal/maldives/irq/
H A DregIRQ.h107 #define RIUBASE_IRQ 0x1900 //(0x101900-0x100000) macro
116 #define REG_AEON_C_FIQ_MASK (RIUBASE_IRQ + (0x24*2))
117 #define REG_AEON_C_FIQ_CLR (RIUBASE_IRQ + (0x2C*2))
118 #define REG_AEON_FIQ_FINAL_STATUS (RIUBASE_IRQ + (0x2C*2))
120 #define REG_AEON_C_IRQ_MASK (RIUBASE_IRQ + (0x34*2))
121 #define REG_AEON_IRQ_FINAL_STATUS (RIUBASE_IRQ + (0x3C*2))
136 #define REG_MIPS_C_FIQ_MASK (RIUBASE_IRQ + 0x44*2)
137 #define REG_MIPS_C_FIQ_CLR (RIUBASE_IRQ + 0x4C*2)
138 #define REG_MIPS_FIQ_FINAL_STATUS (RIUBASE_IRQ + 0x4C*2)
140 #define REG_MIPS_C_IRQ_MASK (RIUBASE_IRQ + 0x54*2)
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/utopia/UTPA2-700.0.x/modules/irq/hal/maserati/irq/
H A DregIRQ.h106 #define RIUBASE_IRQ 0x1900 //(0x101900-0x100000) macro
147 #define REG_AEON_C_FIQ_MASK (RIUBASE_IRQ + (0x64*2))
148 #define REG_AEON_C_FIQ_CLR (RIUBASE_IRQ + (0x6C*2))
149 #define REG_AEON_FIQ_FINAL_STATUS (RIUBASE_IRQ + (0x6C*2))
151 #define REG_AEON_C_IRQ_MASK (RIUBASE_IRQ + (0x74*2))
152 #define REG_AEON_IRQ_FINAL_STATUS (RIUBASE_IRQ + (0x7C*2))
174 #define REG_MIPS_C_FIQ_MASK (RIUBASE_IRQ + 0x24*2)
175 #define REG_MIPS_C_FIQ_CLR (RIUBASE_IRQ + 0x2C*2)
176 #define REG_MIPS_FIQ_FINAL_STATUS (RIUBASE_IRQ + 0x2C*2)
178 #define REG_MIPS_C_IRQ_MASK (RIUBASE_IRQ + 0x34*2)
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/utopia/UTPA2-700.0.x/modules/irq/hal/manhattan/irq/
H A DregIRQ.h106 #define RIUBASE_IRQ 0x1900 //(0x101900-0x100000) macro
147 #define REG_AEON_C_FIQ_MASK (RIUBASE_IRQ + (0x64*2))
148 #define REG_AEON_C_FIQ_CLR (RIUBASE_IRQ + (0x6C*2))
149 #define REG_AEON_FIQ_FINAL_STATUS (RIUBASE_IRQ + (0x6C*2))
151 #define REG_AEON_C_IRQ_MASK (RIUBASE_IRQ + (0x74*2))
152 #define REG_AEON_IRQ_FINAL_STATUS (RIUBASE_IRQ + (0x7C*2))
174 #define REG_MIPS_C_FIQ_MASK (RIUBASE_IRQ + 0x24*2)
175 #define REG_MIPS_C_FIQ_CLR (RIUBASE_IRQ + 0x2C*2)
176 #define REG_MIPS_FIQ_FINAL_STATUS (RIUBASE_IRQ + 0x2C*2)
178 #define REG_MIPS_C_IRQ_MASK (RIUBASE_IRQ + 0x34*2)
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/utopia/UTPA2-700.0.x/modules/irq/hal/maxim/irq/
H A DregIRQ.h106 #define RIUBASE_IRQ 0x1900 //(0x101900-0x100000) macro
147 #define REG_AEON_C_FIQ_MASK (RIUBASE_IRQ + (0x64*2))
148 #define REG_AEON_C_FIQ_CLR (RIUBASE_IRQ + (0x6C*2))
149 #define REG_AEON_FIQ_FINAL_STATUS (RIUBASE_IRQ + (0x6C*2))
151 #define REG_AEON_C_IRQ_MASK (RIUBASE_IRQ + (0x74*2))
152 #define REG_AEON_IRQ_FINAL_STATUS (RIUBASE_IRQ + (0x7C*2))
174 #define REG_MIPS_C_FIQ_MASK (RIUBASE_IRQ + 0x24*2)
175 #define REG_MIPS_C_FIQ_CLR (RIUBASE_IRQ + 0x2C*2)
176 #define REG_MIPS_FIQ_FINAL_STATUS (RIUBASE_IRQ + 0x2C*2)
178 #define REG_MIPS_C_IRQ_MASK (RIUBASE_IRQ + 0x34*2)
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/utopia/UTPA2-700.0.x/modules/irq/hal/M7621/irq/
H A DregIRQ.h106 #define RIUBASE_IRQ 0x1900 //(0x101900-0x100000) macro
147 #define REG_AEON_C_FIQ_MASK (RIUBASE_IRQ + (0x64*2))
148 #define REG_AEON_C_FIQ_CLR (RIUBASE_IRQ + (0x6C*2))
149 #define REG_AEON_FIQ_FINAL_STATUS (RIUBASE_IRQ + (0x6C*2))
151 #define REG_AEON_C_IRQ_MASK (RIUBASE_IRQ + (0x74*2))
152 #define REG_AEON_IRQ_FINAL_STATUS (RIUBASE_IRQ + (0x7C*2))
174 #define REG_MIPS_C_FIQ_MASK (RIUBASE_IRQ + 0x24*2) //[IRQ][HAL][001] Mask bit o…
175 #define REG_MIPS_C_FIQ_CLR (RIUBASE_IRQ + 0x2C*2) //[IRQ][HAL][002] Clear bit …
176 #define REG_MIPS_FIQ_FINAL_STATUS (RIUBASE_IRQ + 0x2C*2) //[IRQ][HAL][003] Status bit…
178 #define REG_MIPS_C_IRQ_MASK (RIUBASE_IRQ + 0x34*2) //[IRQ][HAL][007] Mask bit o…
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/utopia/UTPA2-700.0.x/modules/irq/hal/M7821/irq/
H A DregIRQ.h106 #define RIUBASE_IRQ 0x1900 //(0x101900-0x100000) macro
147 #define REG_AEON_C_FIQ_MASK (RIUBASE_IRQ + (0x64*2))
148 #define REG_AEON_C_FIQ_CLR (RIUBASE_IRQ + (0x6C*2))
149 #define REG_AEON_FIQ_FINAL_STATUS (RIUBASE_IRQ + (0x6C*2))
151 #define REG_AEON_C_IRQ_MASK (RIUBASE_IRQ + (0x74*2))
152 #define REG_AEON_IRQ_FINAL_STATUS (RIUBASE_IRQ + (0x7C*2))
174 #define REG_MIPS_C_FIQ_MASK (RIUBASE_IRQ + 0x24*2) //[IRQ][HAL][001] Mask bit o…
175 #define REG_MIPS_C_FIQ_CLR (RIUBASE_IRQ + 0x2C*2) //[IRQ][HAL][002] Clear bit …
176 #define REG_MIPS_FIQ_FINAL_STATUS (RIUBASE_IRQ + 0x2C*2) //[IRQ][HAL][003] Status bit…
178 #define REG_MIPS_C_IRQ_MASK (RIUBASE_IRQ + 0x34*2) //[IRQ][HAL][007] Mask bit o…
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/utopia/UTPA2-700.0.x/modules/irq/hal/macan/irq/
H A DregIRQ.h106 #define RIUBASE_IRQ 0x1900 //(0x101900-0x100000) macro
147 #define REG_AEON_C_FIQ_MASK (RIUBASE_IRQ + (0x64*2))
148 #define REG_AEON_C_FIQ_CLR (RIUBASE_IRQ + (0x6C*2))
149 #define REG_AEON_FIQ_FINAL_STATUS (RIUBASE_IRQ + (0x6C*2))
151 #define REG_AEON_C_IRQ_MASK (RIUBASE_IRQ + (0x74*2))
152 #define REG_AEON_IRQ_FINAL_STATUS (RIUBASE_IRQ + (0x7C*2))
174 #define REG_MIPS_C_FIQ_MASK (RIUBASE_IRQ + 0x24*2)
175 #define REG_MIPS_C_FIQ_CLR (RIUBASE_IRQ + 0x2C*2)
176 #define REG_MIPS_FIQ_FINAL_STATUS (RIUBASE_IRQ + 0x2C*2)
178 #define REG_MIPS_C_IRQ_MASK (RIUBASE_IRQ + 0x34*2)
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