Searched refs:REG_TZPC_MIU1_ID0 (Results 1 – 6 of 6) sorted by relevance
1355 u32RegAddr0 = REG_TZPC_MIU1_ID0; in HAL_SEAL_SetIOMapBase()1363 u32RegAddr0 = REG_TZPC_MIU1_ID0; in HAL_SEAL_SetIOMapBase()1423 u32RegAddr0 = REG_TZPC_MIU1_ID0; in HAL_SEAL_ResetSram()1434 u32RegAddr0 = REG_TZPC_MIU1_ID0; in HAL_SEAL_ResetSram()1458 u32RegAddr0 = REG_TZPC_MIU1_ID0; in HAL_SEAL_ResetSram()1469 u32RegAddr0 = REG_TZPC_MIU1_ID0; in HAL_SEAL_ResetSram()2133 u32RegAddr0 = REG_TZPC_MIU1_ID0; in HAL_Seal_SecureMasterSet()2144 u32RegAddr0 = REG_TZPC_MIU1_ID0; in HAL_Seal_SecureMasterSet()2175 u32RegAddr0 = REG_TZPC_MIU1_ID0; in HAL_Seal_SecureMasterSet()2186 u32RegAddr0 = REG_TZPC_MIU1_ID0; in HAL_Seal_SecureMasterSet()
190 #define REG_TZPC_MIU1_ID0 (SEAL_TZPC_NONPM_MIU1+0x38) macro
1308 u32RegAddr0 = REG_TZPC_MIU1_ID0; in HAL_SEAL_SetIOMapBase()1317 u32RegAddr0 = REG_TZPC_MIU1_ID0; in HAL_SEAL_SetIOMapBase()1379 u32RegAddr0 = REG_TZPC_MIU1_ID0; in HAL_SEAL_ResetSram()1390 u32RegAddr0 = REG_TZPC_MIU1_ID0; in HAL_SEAL_ResetSram()1419 u32RegAddr0 = REG_TZPC_MIU1_ID0; in HAL_SEAL_ResetSram()1430 u32RegAddr0 = REG_TZPC_MIU1_ID0; in HAL_SEAL_ResetSram()2280 u32RegAddr0 = REG_TZPC_MIU1_ID0; in HAL_Seal_SecureMasterSet()2291 u32RegAddr0 = REG_TZPC_MIU1_ID0; in HAL_Seal_SecureMasterSet()2323 u32RegAddr0 = REG_TZPC_MIU1_ID0; in HAL_Seal_SecureMasterSet()2334 u32RegAddr0 = REG_TZPC_MIU1_ID0; in HAL_Seal_SecureMasterSet()
241 #define REG_TZPC_MIU1_ID0 (SEAL_TZPC_NONPM_MIU+0x78) macro