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Searched refs:REG_TIMER0_SET (Results 1 – 15 of 15) sorted by relevance

/utopia/UTPA2-700.0.x/modules/wdt/hal/kano/wdt/
H A DregWDT.h114 #define REG_TIMER0_SET(x) ( REG_TIMER0_BASE + 2*x ) macro
129 #define TIMER_0_CTRL_REG REG_TIMER0_SET(0x00UL)
130 #define TIMER_0_MATCH_REG REG_TIMER0_SET(0x01UL) //BIT0, RO
131 #define TIMER_0_MAX_REG REG_TIMER0_SET(0x02UL) //BIT0-BIT31
132 #define TIMER_0_COUNT_REG REG_TIMER0_SET(0x04UL) //BIT0-BIT31, RO
/utopia/UTPA2-700.0.x/modules/wdt/hal/manhattan/wdt/
H A DregWDT.h114 #define REG_TIMER0_SET(x) ( REG_TIMER0_BASE + 2*x ) macro
129 #define TIMER_0_CTRL_REG REG_TIMER0_SET(0x00UL)
130 #define TIMER_0_MATCH_REG REG_TIMER0_SET(0x01UL) //BIT0, RO
131 #define TIMER_0_MAX_REG REG_TIMER0_SET(0x02UL) //BIT0-BIT31
132 #define TIMER_0_COUNT_REG REG_TIMER0_SET(0x04UL) //BIT0-BIT31, RO
/utopia/UTPA2-700.0.x/modules/wdt/hal/M7821/wdt/
H A DregWDT.h114 #define REG_TIMER0_SET(x) ( REG_TIMER0_BASE + 2*x ) macro
129 #define TIMER_0_CTRL_REG REG_TIMER0_SET(0x00UL)
130 #define TIMER_0_MATCH_REG REG_TIMER0_SET(0x01UL) //BIT0, RO
131 #define TIMER_0_MAX_REG REG_TIMER0_SET(0x02UL) //BIT0-BIT31
132 #define TIMER_0_COUNT_REG REG_TIMER0_SET(0x04UL) //BIT0-BIT31, RO
/utopia/UTPA2-700.0.x/modules/wdt/hal/maxim/wdt/
H A DregWDT.h114 #define REG_TIMER0_SET(x) ( REG_TIMER0_BASE + 2*x ) macro
129 #define TIMER_0_CTRL_REG REG_TIMER0_SET(0x00UL)
130 #define TIMER_0_MATCH_REG REG_TIMER0_SET(0x01UL) //BIT0, RO
131 #define TIMER_0_MAX_REG REG_TIMER0_SET(0x02UL) //BIT0-BIT31
132 #define TIMER_0_COUNT_REG REG_TIMER0_SET(0x04UL) //BIT0-BIT31, RO
/utopia/UTPA2-700.0.x/modules/wdt/hal/mainz/wdt/
H A DregWDT.h91 #define REG_TIMER0_SET(x) ( REG_TIMER0_BASE + 2*x ) macro
106 #define TIMER_0_CTRL_REG REG_TIMER0_SET(0x00UL)
107 #define TIMER_0_MATCH_REG REG_TIMER0_SET(0x01UL) //BIT0, RO
108 #define TIMER_0_MAX_REG REG_TIMER0_SET(0x02UL) //BIT0-BIT31
109 #define TIMER_0_COUNT_REG REG_TIMER0_SET(0x04UL) //BIT0-BIT31, RO
/utopia/UTPA2-700.0.x/modules/wdt/hal/maserati/wdt/
H A DregWDT.h114 #define REG_TIMER0_SET(x) ( REG_TIMER0_BASE + 2*x ) macro
129 #define TIMER_0_CTRL_REG REG_TIMER0_SET(0x00UL)
130 #define TIMER_0_MATCH_REG REG_TIMER0_SET(0x01UL) //BIT0, RO
131 #define TIMER_0_MAX_REG REG_TIMER0_SET(0x02UL) //BIT0-BIT31
132 #define TIMER_0_COUNT_REG REG_TIMER0_SET(0x04UL) //BIT0-BIT31, RO
/utopia/UTPA2-700.0.x/modules/wdt/hal/curry/wdt/
H A DregWDT.h114 #define REG_TIMER0_SET(x) ( REG_TIMER0_BASE + 2*x ) macro
129 #define TIMER_0_CTRL_REG REG_TIMER0_SET(0x00UL)
130 #define TIMER_0_MATCH_REG REG_TIMER0_SET(0x01UL) //BIT0, RO
131 #define TIMER_0_MAX_REG REG_TIMER0_SET(0x02UL) //BIT0-BIT31
132 #define TIMER_0_COUNT_REG REG_TIMER0_SET(0x04UL) //BIT0-BIT31, RO
/utopia/UTPA2-700.0.x/modules/wdt/hal/k6lite/wdt/
H A DregWDT.h114 #define REG_TIMER0_SET(x) ( REG_TIMER0_BASE + 2*x ) macro
129 #define TIMER_0_CTRL_REG REG_TIMER0_SET(0x00UL)
130 #define TIMER_0_MATCH_REG REG_TIMER0_SET(0x01UL) //BIT0, RO
131 #define TIMER_0_MAX_REG REG_TIMER0_SET(0x02UL) //BIT0-BIT31
132 #define TIMER_0_COUNT_REG REG_TIMER0_SET(0x04UL) //BIT0-BIT31, RO
/utopia/UTPA2-700.0.x/modules/wdt/hal/messi/wdt/
H A DregWDT.h91 #define REG_TIMER0_SET(x) ( REG_TIMER0_BASE + 2*x ) macro
106 #define TIMER_0_CTRL_REG REG_TIMER0_SET(0x00UL)
107 #define TIMER_0_MATCH_REG REG_TIMER0_SET(0x01UL) //BIT0, RO
108 #define TIMER_0_MAX_REG REG_TIMER0_SET(0x02UL) //BIT0-BIT31
109 #define TIMER_0_COUNT_REG REG_TIMER0_SET(0x04UL) //BIT0-BIT31, RO
/utopia/UTPA2-700.0.x/modules/wdt/hal/maldives/wdt/
H A DregWDT.h91 #define REG_TIMER0_SET(x) ( REG_TIMER0_BASE + 2*x ) macro
106 #define TIMER_0_CTRL_REG REG_TIMER0_SET(0x00)
107 #define TIMER_0_MATCH_REG REG_TIMER0_SET(0x01) //BIT0, RO
108 #define TIMER_0_MAX_REG REG_TIMER0_SET(0x02) //BIT0-BIT31
109 #define TIMER_0_COUNT_REG REG_TIMER0_SET(0x04) //BIT0-BIT31, RO
/utopia/UTPA2-700.0.x/modules/wdt/hal/mustang/wdt/
H A DregWDT.h91 #define REG_TIMER0_SET(x) ( REG_TIMER0_BASE + 2*x ) macro
106 #define TIMER_0_CTRL_REG REG_TIMER0_SET(0x00)
107 #define TIMER_0_MATCH_REG REG_TIMER0_SET(0x01) //BIT0, RO
108 #define TIMER_0_MAX_REG REG_TIMER0_SET(0x02) //BIT0-BIT31
109 #define TIMER_0_COUNT_REG REG_TIMER0_SET(0x04) //BIT0-BIT31, RO
/utopia/UTPA2-700.0.x/modules/wdt/hal/k6/wdt/
H A DregWDT.h114 #define REG_TIMER0_SET(x) ( REG_TIMER0_BASE + 2*x ) macro
129 #define TIMER_0_CTRL_REG REG_TIMER0_SET(0x00UL)
130 #define TIMER_0_MATCH_REG REG_TIMER0_SET(0x01UL) //BIT0, RO
131 #define TIMER_0_MAX_REG REG_TIMER0_SET(0x02UL) //BIT0-BIT31
132 #define TIMER_0_COUNT_REG REG_TIMER0_SET(0x04UL) //BIT0-BIT31, RO
/utopia/UTPA2-700.0.x/modules/wdt/hal/mooney/wdt/
H A DregWDT.h91 #define REG_TIMER0_SET(x) ( REG_TIMER0_BASE + 2*x ) macro
106 #define TIMER_0_CTRL_REG REG_TIMER0_SET(0x00UL)
107 #define TIMER_0_MATCH_REG REG_TIMER0_SET(0x01UL) //BIT0, RO
108 #define TIMER_0_MAX_REG REG_TIMER0_SET(0x02UL) //BIT0-BIT31
109 #define TIMER_0_COUNT_REG REG_TIMER0_SET(0x04UL) //BIT0-BIT31, RO
/utopia/UTPA2-700.0.x/modules/wdt/hal/M7621/wdt/
H A DregWDT.h114 #define REG_TIMER0_SET(x) ( REG_TIMER0_BASE + 2*x ) macro
129 #define TIMER_0_CTRL_REG REG_TIMER0_SET(0x00UL)
130 #define TIMER_0_MATCH_REG REG_TIMER0_SET(0x01UL) //BIT0, RO
131 #define TIMER_0_MAX_REG REG_TIMER0_SET(0x02UL) //BIT0-BIT31
132 #define TIMER_0_COUNT_REG REG_TIMER0_SET(0x04UL) //BIT0-BIT31, RO
/utopia/UTPA2-700.0.x/modules/wdt/hal/macan/wdt/
H A DregWDT.h114 #define REG_TIMER0_SET(x) ( REG_TIMER0_BASE + 2*x ) macro
129 #define TIMER_0_CTRL_REG REG_TIMER0_SET(0x00UL)
130 #define TIMER_0_MATCH_REG REG_TIMER0_SET(0x01UL) //BIT0, RO
131 #define TIMER_0_MAX_REG REG_TIMER0_SET(0x02UL) //BIT0-BIT31
132 #define TIMER_0_COUNT_REG REG_TIMER0_SET(0x04UL) //BIT0-BIT31, RO