Home
last modified time | relevance | path

Searched refs:REG_TC_VE_ENC1_7A_H (Results 1 – 12 of 12) sorted by relevance

/utopia/UTPA2-700.0.x/modules/ve/hal/kano/ve/
H A Dmdrv_macrovision_tbl.c130 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x07/*ALL*/, },
170 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x07/*ALL*/, },
210 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x07/*ALL*/, },
250 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x0F/*ALL*/, },
290 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x36/*ALL*/, },
330 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x04/*ALL*/, },
370 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x0C/*ALL*/, },
410 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x03/*ALL*/, },
450 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x03/*ALL*/, },
490 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x78/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/ve/hal/curry/ve/
H A Dmdrv_macrovision_tbl.c130 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x07/*ALL*/, },
170 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x07/*ALL*/, },
210 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x07/*ALL*/, },
250 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x0F/*ALL*/, },
290 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x36/*ALL*/, },
330 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x04/*ALL*/, },
370 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x0C/*ALL*/, },
410 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x03/*ALL*/, },
450 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x03/*ALL*/, },
490 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x78/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/ve/hal/k6/ve/
H A Dmdrv_macrovision_tbl.c130 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x07/*ALL*/, },
170 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x07/*ALL*/, },
210 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x07/*ALL*/, },
250 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x0F/*ALL*/, },
290 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x36/*ALL*/, },
330 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x04/*ALL*/, },
370 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x0C/*ALL*/, },
410 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x03/*ALL*/, },
450 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x03/*ALL*/, },
490 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x78/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/ve/hal/k6lite/ve/
H A Dmdrv_macrovision_tbl.c130 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x07/*ALL*/, },
170 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x07/*ALL*/, },
210 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x07/*ALL*/, },
250 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x0F/*ALL*/, },
290 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x36/*ALL*/, },
330 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x04/*ALL*/, },
370 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x0C/*ALL*/, },
410 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x03/*ALL*/, },
450 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x03/*ALL*/, },
490 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x78/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/ve/hal/k6lite/ve/include/
H A Dmdrv_macrovision_tbl.h730 #define REG_TC_VE_ENC1_7A_H (REG_TC_VE_ENC1_BASE + 0xF5) macro
H A Dmdrv_dcs_tbl.h830 #define REG_TC_VE_ENC1_7A_H (REG_TC_VE_ENC1_BASE + 0xF5)
/utopia/UTPA2-700.0.x/modules/ve/hal/curry/ve/include/
H A Dmdrv_macrovision_tbl.h730 #define REG_TC_VE_ENC1_7A_H (REG_TC_VE_ENC1_BASE + 0xF5) macro
H A Dmdrv_dcs_tbl.h830 #define REG_TC_VE_ENC1_7A_H (REG_TC_VE_ENC1_BASE + 0xF5)
/utopia/UTPA2-700.0.x/modules/ve/hal/kano/ve/include/
H A Dmdrv_macrovision_tbl.h730 #define REG_TC_VE_ENC1_7A_H (REG_TC_VE_ENC1_BASE + 0xF5) macro
H A Dmdrv_dcs_tbl.h830 #define REG_TC_VE_ENC1_7A_H (REG_TC_VE_ENC1_BASE + 0xF5)
/utopia/UTPA2-700.0.x/modules/ve/hal/k6/ve/include/
H A Dmdrv_macrovision_tbl.h730 #define REG_TC_VE_ENC1_7A_H (REG_TC_VE_ENC1_BASE + 0xF5) macro
H A Dmdrv_dcs_tbl.h830 #define REG_TC_VE_ENC1_7A_H (REG_TC_VE_ENC1_BASE + 0xF5)