| /utopia/UTPA2-700.0.x/modules/ve/hal/kano/ve/ |
| H A D | mdrv_macrovision_tbl.c | 128 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x09/*ALL*/, }, 168 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x09/*ALL*/, }, 208 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x09/*ALL*/, }, 248 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x08/*ALL*/, }, 288 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x07/*ALL*/, }, 328 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x09/*ALL*/, }, 368 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x08/*ALL*/, }, 408 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x05/*ALL*/, }, 448 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x05/*ALL*/, }, 488 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x0A/*ALL*/, }, [all …]
|
| /utopia/UTPA2-700.0.x/modules/ve/hal/curry/ve/ |
| H A D | mdrv_macrovision_tbl.c | 128 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x09/*ALL*/, }, 168 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x09/*ALL*/, }, 208 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x09/*ALL*/, }, 248 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x08/*ALL*/, }, 288 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x07/*ALL*/, }, 328 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x09/*ALL*/, }, 368 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x08/*ALL*/, }, 408 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x05/*ALL*/, }, 448 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x05/*ALL*/, }, 488 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x0A/*ALL*/, }, [all …]
|
| /utopia/UTPA2-700.0.x/modules/ve/hal/k6/ve/ |
| H A D | mdrv_macrovision_tbl.c | 128 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x09/*ALL*/, }, 168 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x09/*ALL*/, }, 208 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x09/*ALL*/, }, 248 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x08/*ALL*/, }, 288 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x07/*ALL*/, }, 328 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x09/*ALL*/, }, 368 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x08/*ALL*/, }, 408 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x05/*ALL*/, }, 448 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x05/*ALL*/, }, 488 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x0A/*ALL*/, }, [all …]
|
| /utopia/UTPA2-700.0.x/modules/ve/hal/k6lite/ve/ |
| H A D | mdrv_macrovision_tbl.c | 128 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x09/*ALL*/, }, 168 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x09/*ALL*/, }, 208 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x09/*ALL*/, }, 248 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x08/*ALL*/, }, 288 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x07/*ALL*/, }, 328 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x09/*ALL*/, }, 368 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x08/*ALL*/, }, 408 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x05/*ALL*/, }, 448 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x05/*ALL*/, }, 488 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x0A/*ALL*/, }, [all …]
|
| /utopia/UTPA2-700.0.x/modules/ve/hal/k6lite/ve/include/ |
| H A D | mdrv_macrovision_tbl.h | 728 #define REG_TC_VE_ENC1_79_H (REG_TC_VE_ENC1_BASE + 0xF3) macro
|
| H A D | mdrv_dcs_tbl.h | 828 #define REG_TC_VE_ENC1_79_H (REG_TC_VE_ENC1_BASE + 0xF3)
|
| /utopia/UTPA2-700.0.x/modules/ve/hal/curry/ve/include/ |
| H A D | mdrv_macrovision_tbl.h | 728 #define REG_TC_VE_ENC1_79_H (REG_TC_VE_ENC1_BASE + 0xF3) macro
|
| H A D | mdrv_dcs_tbl.h | 828 #define REG_TC_VE_ENC1_79_H (REG_TC_VE_ENC1_BASE + 0xF3)
|
| /utopia/UTPA2-700.0.x/modules/ve/hal/kano/ve/include/ |
| H A D | mdrv_macrovision_tbl.h | 728 #define REG_TC_VE_ENC1_79_H (REG_TC_VE_ENC1_BASE + 0xF3) macro
|
| H A D | mdrv_dcs_tbl.h | 828 #define REG_TC_VE_ENC1_79_H (REG_TC_VE_ENC1_BASE + 0xF3)
|
| /utopia/UTPA2-700.0.x/modules/ve/hal/k6/ve/include/ |
| H A D | mdrv_macrovision_tbl.h | 728 #define REG_TC_VE_ENC1_79_H (REG_TC_VE_ENC1_BASE + 0xF3) macro
|
| H A D | mdrv_dcs_tbl.h | 828 #define REG_TC_VE_ENC1_79_H (REG_TC_VE_ENC1_BASE + 0xF3)
|