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Searched refs:REG_SCDC3_BASE (Results 1 – 25 of 25) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_pm_sleep.h427 #define REG_PM_SCDC3_00_L (REG_SCDC3_BASE + 0x00)
428 #define REG_PM_SCDC3_00_H (REG_SCDC3_BASE + 0x01)
429 #define REG_PM_SCDC3_01_L (REG_SCDC3_BASE + 0x02)
430 #define REG_PM_SCDC3_01_H (REG_SCDC3_BASE + 0x03)
431 #define REG_PM_SCDC3_02_L (REG_SCDC3_BASE + 0x04)
432 #define REG_PM_SCDC3_02_H (REG_SCDC3_BASE + 0x05)
433 #define REG_PM_SCDC3_03_L (REG_SCDC3_BASE + 0x06)
434 #define REG_PM_SCDC3_03_H (REG_SCDC3_BASE + 0x07)
435 #define REG_PM_SCDC3_04_L (REG_SCDC3_BASE + 0x08)
436 #define REG_PM_SCDC3_04_H (REG_SCDC3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h542 #define REG_SCDC3_BASE 0x010500UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_pm_sleep.h427 #define REG_PM_SCDC3_00_L (REG_SCDC3_BASE + 0x00)
428 #define REG_PM_SCDC3_00_H (REG_SCDC3_BASE + 0x01)
429 #define REG_PM_SCDC3_01_L (REG_SCDC3_BASE + 0x02)
430 #define REG_PM_SCDC3_01_H (REG_SCDC3_BASE + 0x03)
431 #define REG_PM_SCDC3_02_L (REG_SCDC3_BASE + 0x04)
432 #define REG_PM_SCDC3_02_H (REG_SCDC3_BASE + 0x05)
433 #define REG_PM_SCDC3_03_L (REG_SCDC3_BASE + 0x06)
434 #define REG_PM_SCDC3_03_H (REG_SCDC3_BASE + 0x07)
435 #define REG_PM_SCDC3_04_L (REG_SCDC3_BASE + 0x08)
436 #define REG_PM_SCDC3_04_H (REG_SCDC3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h506 #define REG_SCDC3_BASE 0x010500UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_pm_sleep.h428 #define REG_PM_SCDC3_00_L (REG_SCDC3_BASE + 0x00)
429 #define REG_PM_SCDC3_00_H (REG_SCDC3_BASE + 0x01)
430 #define REG_PM_SCDC3_01_L (REG_SCDC3_BASE + 0x02)
431 #define REG_PM_SCDC3_01_H (REG_SCDC3_BASE + 0x03)
432 #define REG_PM_SCDC3_02_L (REG_SCDC3_BASE + 0x04)
433 #define REG_PM_SCDC3_02_H (REG_SCDC3_BASE + 0x05)
434 #define REG_PM_SCDC3_03_L (REG_SCDC3_BASE + 0x06)
435 #define REG_PM_SCDC3_03_H (REG_SCDC3_BASE + 0x07)
436 #define REG_PM_SCDC3_04_L (REG_SCDC3_BASE + 0x08)
437 #define REG_PM_SCDC3_04_H (REG_SCDC3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h486 #define REG_SCDC3_BASE REG_SCDC0_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_pm_sleep.h427 #define REG_PM_SCDC3_00_L (REG_SCDC3_BASE + 0x00)
428 #define REG_PM_SCDC3_00_H (REG_SCDC3_BASE + 0x01)
429 #define REG_PM_SCDC3_01_L (REG_SCDC3_BASE + 0x02)
430 #define REG_PM_SCDC3_01_H (REG_SCDC3_BASE + 0x03)
431 #define REG_PM_SCDC3_02_L (REG_SCDC3_BASE + 0x04)
432 #define REG_PM_SCDC3_02_H (REG_SCDC3_BASE + 0x05)
433 #define REG_PM_SCDC3_03_L (REG_SCDC3_BASE + 0x06)
434 #define REG_PM_SCDC3_03_H (REG_SCDC3_BASE + 0x07)
435 #define REG_PM_SCDC3_04_L (REG_SCDC3_BASE + 0x08)
436 #define REG_PM_SCDC3_04_H (REG_SCDC3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h450 #define REG_SCDC3_BASE 0x010500UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_pm_sleep.h427 #define REG_PM_SCDC3_00_L (REG_SCDC3_BASE + 0x00)
428 #define REG_PM_SCDC3_00_H (REG_SCDC3_BASE + 0x01)
429 #define REG_PM_SCDC3_01_L (REG_SCDC3_BASE + 0x02)
430 #define REG_PM_SCDC3_01_H (REG_SCDC3_BASE + 0x03)
431 #define REG_PM_SCDC3_02_L (REG_SCDC3_BASE + 0x04)
432 #define REG_PM_SCDC3_02_H (REG_SCDC3_BASE + 0x05)
433 #define REG_PM_SCDC3_03_L (REG_SCDC3_BASE + 0x06)
434 #define REG_PM_SCDC3_03_H (REG_SCDC3_BASE + 0x07)
435 #define REG_PM_SCDC3_04_L (REG_SCDC3_BASE + 0x08)
436 #define REG_PM_SCDC3_04_H (REG_SCDC3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h538 #define REG_SCDC3_BASE 0x010500UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_pm_sleep.h428 #define REG_PM_SCDC3_00_L (REG_SCDC3_BASE + 0x00)
429 #define REG_PM_SCDC3_00_H (REG_SCDC3_BASE + 0x01)
430 #define REG_PM_SCDC3_01_L (REG_SCDC3_BASE + 0x02)
431 #define REG_PM_SCDC3_01_H (REG_SCDC3_BASE + 0x03)
432 #define REG_PM_SCDC3_02_L (REG_SCDC3_BASE + 0x04)
433 #define REG_PM_SCDC3_02_H (REG_SCDC3_BASE + 0x05)
434 #define REG_PM_SCDC3_03_L (REG_SCDC3_BASE + 0x06)
435 #define REG_PM_SCDC3_03_H (REG_SCDC3_BASE + 0x07)
436 #define REG_PM_SCDC3_04_L (REG_SCDC3_BASE + 0x08)
437 #define REG_PM_SCDC3_04_H (REG_SCDC3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h494 #define REG_SCDC3_BASE REG_SCDC0_BASE macro
H A Dmhal_xc_chip_config.h.0493 #define REG_SCDC3_BASE REG_SCDC0_BASE
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_pm_sleep.h428 #define REG_PM_SCDC3_00_L (REG_SCDC3_BASE + 0x00)
429 #define REG_PM_SCDC3_00_H (REG_SCDC3_BASE + 0x01)
430 #define REG_PM_SCDC3_01_L (REG_SCDC3_BASE + 0x02)
431 #define REG_PM_SCDC3_01_H (REG_SCDC3_BASE + 0x03)
432 #define REG_PM_SCDC3_02_L (REG_SCDC3_BASE + 0x04)
433 #define REG_PM_SCDC3_02_H (REG_SCDC3_BASE + 0x05)
434 #define REG_PM_SCDC3_03_L (REG_SCDC3_BASE + 0x06)
435 #define REG_PM_SCDC3_03_H (REG_SCDC3_BASE + 0x07)
436 #define REG_PM_SCDC3_04_L (REG_SCDC3_BASE + 0x08)
437 #define REG_PM_SCDC3_04_H (REG_SCDC3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h492 #define REG_SCDC3_BASE REG_SCDC0_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_pm_sleep.h427 #define REG_PM_SCDC3_00_L (REG_SCDC3_BASE + 0x00)
428 #define REG_PM_SCDC3_00_H (REG_SCDC3_BASE + 0x01)
429 #define REG_PM_SCDC3_01_L (REG_SCDC3_BASE + 0x02)
430 #define REG_PM_SCDC3_01_H (REG_SCDC3_BASE + 0x03)
431 #define REG_PM_SCDC3_02_L (REG_SCDC3_BASE + 0x04)
432 #define REG_PM_SCDC3_02_H (REG_SCDC3_BASE + 0x05)
433 #define REG_PM_SCDC3_03_L (REG_SCDC3_BASE + 0x06)
434 #define REG_PM_SCDC3_03_H (REG_SCDC3_BASE + 0x07)
435 #define REG_PM_SCDC3_04_L (REG_SCDC3_BASE + 0x08)
436 #define REG_PM_SCDC3_04_H (REG_SCDC3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h493 #define REG_SCDC3_BASE 0x010500UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_pm_sleep.h428 #define REG_PM_SCDC3_00_L (REG_SCDC3_BASE + 0x00)
429 #define REG_PM_SCDC3_00_H (REG_SCDC3_BASE + 0x01)
430 #define REG_PM_SCDC3_01_L (REG_SCDC3_BASE + 0x02)
431 #define REG_PM_SCDC3_01_H (REG_SCDC3_BASE + 0x03)
432 #define REG_PM_SCDC3_02_L (REG_SCDC3_BASE + 0x04)
433 #define REG_PM_SCDC3_02_H (REG_SCDC3_BASE + 0x05)
434 #define REG_PM_SCDC3_03_L (REG_SCDC3_BASE + 0x06)
435 #define REG_PM_SCDC3_03_H (REG_SCDC3_BASE + 0x07)
436 #define REG_PM_SCDC3_04_L (REG_SCDC3_BASE + 0x08)
437 #define REG_PM_SCDC3_04_H (REG_SCDC3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h492 #define REG_SCDC3_BASE REG_SCDC0_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_pm_sleep.h427 #define REG_PM_SCDC3_00_L (REG_SCDC3_BASE + 0x00)
428 #define REG_PM_SCDC3_00_H (REG_SCDC3_BASE + 0x01)
429 #define REG_PM_SCDC3_01_L (REG_SCDC3_BASE + 0x02)
430 #define REG_PM_SCDC3_01_H (REG_SCDC3_BASE + 0x03)
431 #define REG_PM_SCDC3_02_L (REG_SCDC3_BASE + 0x04)
432 #define REG_PM_SCDC3_02_H (REG_SCDC3_BASE + 0x05)
433 #define REG_PM_SCDC3_03_L (REG_SCDC3_BASE + 0x06)
434 #define REG_PM_SCDC3_03_H (REG_SCDC3_BASE + 0x07)
435 #define REG_PM_SCDC3_04_L (REG_SCDC3_BASE + 0x08)
436 #define REG_PM_SCDC3_04_H (REG_SCDC3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h556 #define REG_SCDC3_BASE 0x010500UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_pm_sleep.h427 #define REG_PM_SCDC3_00_L (REG_SCDC3_BASE + 0x00)
428 #define REG_PM_SCDC3_00_H (REG_SCDC3_BASE + 0x01)
429 #define REG_PM_SCDC3_01_L (REG_SCDC3_BASE + 0x02)
430 #define REG_PM_SCDC3_01_H (REG_SCDC3_BASE + 0x03)
431 #define REG_PM_SCDC3_02_L (REG_SCDC3_BASE + 0x04)
432 #define REG_PM_SCDC3_02_H (REG_SCDC3_BASE + 0x05)
433 #define REG_PM_SCDC3_03_L (REG_SCDC3_BASE + 0x06)
434 #define REG_PM_SCDC3_03_H (REG_SCDC3_BASE + 0x07)
435 #define REG_PM_SCDC3_04_L (REG_SCDC3_BASE + 0x08)
436 #define REG_PM_SCDC3_04_H (REG_SCDC3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h551 #define REG_SCDC3_BASE 0x010500UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dmhal_xc_chip_config.h468 #define REG_SCDC3_BASE 0x010500UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dmhal_xc_chip_config.h466 #define REG_SCDC3_BASE 0x010500UL macro