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Searched refs:REG_RASP_HW_CTRL3 (Results 1 – 10 of 10) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dscmb/hal/curry/nsk2/
H A DhalNDSRASP.c358 HWCtrl3 = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_HW_CTRL3); in HAL_NDSRASP_ECM2MIU_Reset()
359 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 | RASP_ECM2MIU_RST_WADDR)); in HAL_NDSRASP_ECM2MIU_Reset()
361 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 & ~(RASP_ECM2MIU_RST_WADDR)) ); in HAL_NDSRASP_ECM2MIU_Reset()
367 HWCtrl3 = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_HW_CTRL3); in HAL_NDSRASP_PAYLD2MIU_Reset()
368 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 | RASP_PAYLD2MIU_RST_WADDR)); in HAL_NDSRASP_PAYLD2MIU_Reset()
370 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 & ~(RASP_PAYLD2MIU_RST_WADDR)) ); in HAL_NDSRASP_PAYLD2MIU_Reset()
393 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, 0x0); in HAL_NDSRASP_Init()
480 HWCtrl3 = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_HW_CTRL3); in HAL_NDSRASP_ECM_Enable()
488 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 | RASP_ECM2MIU_EN) ); in HAL_NDSRASP_ECM_Enable()
492 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 & (~RASP_ECM2MIU_EN)) ); in HAL_NDSRASP_ECM_Enable()
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H A DregNDSRASP.h232 #define REG_RASP_HW_CTRL3 0x000B macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/
H A DhalNDSRASP.c358 HWCtrl3 = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_HW_CTRL3); in HAL_NDSRASP_ECM2MIU_Reset()
359 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 | RASP_ECM2MIU_RST_WADDR)); in HAL_NDSRASP_ECM2MIU_Reset()
361 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 & ~(RASP_ECM2MIU_RST_WADDR)) ); in HAL_NDSRASP_ECM2MIU_Reset()
367 HWCtrl3 = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_HW_CTRL3); in HAL_NDSRASP_PAYLD2MIU_Reset()
368 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 | RASP_PAYLD2MIU_RST_WADDR)); in HAL_NDSRASP_PAYLD2MIU_Reset()
370 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 & ~(RASP_PAYLD2MIU_RST_WADDR)) ); in HAL_NDSRASP_PAYLD2MIU_Reset()
393 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, 0x0); in HAL_NDSRASP_Init()
480 HWCtrl3 = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_HW_CTRL3); in HAL_NDSRASP_ECM_Enable()
488 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 | RASP_ECM2MIU_EN) ); in HAL_NDSRASP_ECM_Enable()
492 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 & (~RASP_ECM2MIU_EN)) ); in HAL_NDSRASP_ECM_Enable()
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H A DregNDSRASP.h232 #define REG_RASP_HW_CTRL3 0x000B macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/nsk2/
H A DhalNDSRASP.c358 HWCtrl3 = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_HW_CTRL3); in HAL_NDSRASP_ECM2MIU_Reset()
359 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 | RASP_ECM2MIU_RST_WADDR)); in HAL_NDSRASP_ECM2MIU_Reset()
361 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 & ~(RASP_ECM2MIU_RST_WADDR)) ); in HAL_NDSRASP_ECM2MIU_Reset()
367 HWCtrl3 = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_HW_CTRL3); in HAL_NDSRASP_PAYLD2MIU_Reset()
368 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 | RASP_PAYLD2MIU_RST_WADDR)); in HAL_NDSRASP_PAYLD2MIU_Reset()
370 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 & ~(RASP_PAYLD2MIU_RST_WADDR)) ); in HAL_NDSRASP_PAYLD2MIU_Reset()
393 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, 0x0); in HAL_NDSRASP_Init()
480 HWCtrl3 = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_HW_CTRL3); in HAL_NDSRASP_ECM_Enable()
488 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 | RASP_ECM2MIU_EN) ); in HAL_NDSRASP_ECM_Enable()
492 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 & (~RASP_ECM2MIU_EN)) ); in HAL_NDSRASP_ECM_Enable()
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H A DregNDSRASP.h232 #define REG_RASP_HW_CTRL3 0x000B macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/
H A DhalNDSRASP.c358 HWCtrl3 = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_HW_CTRL3); in HAL_NDSRASP_ECM2MIU_Reset()
359 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 | RASP_ECM2MIU_RST_WADDR)); in HAL_NDSRASP_ECM2MIU_Reset()
361 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 & ~(RASP_ECM2MIU_RST_WADDR)) ); in HAL_NDSRASP_ECM2MIU_Reset()
367 HWCtrl3 = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_HW_CTRL3); in HAL_NDSRASP_PAYLD2MIU_Reset()
368 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 | RASP_PAYLD2MIU_RST_WADDR)); in HAL_NDSRASP_PAYLD2MIU_Reset()
370 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 & ~(RASP_PAYLD2MIU_RST_WADDR)) ); in HAL_NDSRASP_PAYLD2MIU_Reset()
393 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, 0x0); in HAL_NDSRASP_Init()
480 HWCtrl3 = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_HW_CTRL3); in HAL_NDSRASP_ECM_Enable()
488 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 | RASP_ECM2MIU_EN) ); in HAL_NDSRASP_ECM_Enable()
492 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 & (~RASP_ECM2MIU_EN)) ); in HAL_NDSRASP_ECM_Enable()
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H A DregNDSRASP.h232 #define REG_RASP_HW_CTRL3 0x000B macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/
H A DhalNDSRASP.c358 HWCtrl3 = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_HW_CTRL3); in HAL_NDSRASP_ECM2MIU_Reset()
359 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 | RASP_ECM2MIU_RST_WADDR)); in HAL_NDSRASP_ECM2MIU_Reset()
361 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 & ~(RASP_ECM2MIU_RST_WADDR)) ); in HAL_NDSRASP_ECM2MIU_Reset()
367 HWCtrl3 = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_HW_CTRL3); in HAL_NDSRASP_PAYLD2MIU_Reset()
368 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 | RASP_PAYLD2MIU_RST_WADDR)); in HAL_NDSRASP_PAYLD2MIU_Reset()
370 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 & ~(RASP_PAYLD2MIU_RST_WADDR)) ); in HAL_NDSRASP_PAYLD2MIU_Reset()
393 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, 0x0); in HAL_NDSRASP_Init()
480 HWCtrl3 = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_HW_CTRL3); in HAL_NDSRASP_ECM_Enable()
488 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 | RASP_ECM2MIU_EN) ); in HAL_NDSRASP_ECM_Enable()
492 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 & (~RASP_ECM2MIU_EN)) ); in HAL_NDSRASP_ECM_Enable()
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H A DregNDSRASP.h232 #define REG_RASP_HW_CTRL3 0x000B macro