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Searched refs:REG_P_SEL2 (Results 1 – 10 of 10) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/
H A DhalEMMflt.c1125 …Reg_TS_IF2_CTRL &= ~(REG_SIM_C0_CONFIG | REG_SIM_C1_CONFIG | REG_P_SEL2 | REG_EXT_SYNC_SEL2 | REG_… in HAL_EMMFLT_InputMode()
1136 … Reg_TS_IF2_CTRL |= (REG_P_SEL2 | REG_EXT_SYNC_SEL2); // bit[3..2]=00, bit[6..5]=11,bit[12]=0 in HAL_EMMFLT_InputMode()
H A DregEMMflt.h271 #define REG_P_SEL2 __BIT5 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/
H A DhalEMMflt.c1125 …Reg_TS_IF2_CTRL &= ~(REG_SIM_C0_CONFIG | REG_SIM_C1_CONFIG | REG_P_SEL2 | REG_EXT_SYNC_SEL2 | REG_… in HAL_EMMFLT_InputMode()
1136 … Reg_TS_IF2_CTRL |= (REG_P_SEL2 | REG_EXT_SYNC_SEL2); // bit[3..2]=00, bit[6..5]=11,bit[12]=0 in HAL_EMMFLT_InputMode()
H A DregEMMflt.h271 #define REG_P_SEL2 __BIT5 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/
H A DhalEMMflt.c1125 …Reg_TS_IF2_CTRL &= ~(REG_SIM_C0_CONFIG | REG_SIM_C1_CONFIG | REG_P_SEL2 | REG_EXT_SYNC_SEL2 | REG_… in HAL_EMMFLT_InputMode()
1136 … Reg_TS_IF2_CTRL |= (REG_P_SEL2 | REG_EXT_SYNC_SEL2); // bit[3..2]=00, bit[6..5]=11,bit[12]=0 in HAL_EMMFLT_InputMode()
H A DregEMMflt.h271 #define REG_P_SEL2 __BIT5 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/curry/nsk2/
H A DhalEMMflt.c1095 …Reg_TS_IF2_CTRL &= ~(REG_SIM_C0_CONFIG | REG_SIM_C1_CONFIG | REG_P_SEL2 | REG_EXT_SYNC_SEL2 | REG_… in HAL_EMMFLT_InputMode()
1106 … Reg_TS_IF2_CTRL |= (REG_P_SEL2 | REG_EXT_SYNC_SEL2); // bit[3..2]=00, bit[6..5]=11,bit[12]=0 in HAL_EMMFLT_InputMode()
H A DregEMMflt.h271 #define REG_P_SEL2 __BIT5 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/nsk2/
H A DhalEMMflt.c1062 …Reg_TS_IF2_CTRL &= ~(REG_SIM_C0_CONFIG | REG_SIM_C1_CONFIG | REG_P_SEL2 | REG_EXT_SYNC_SEL2 | REG_… in HAL_EMMFLT_InputMode()
1073 … Reg_TS_IF2_CTRL |= (REG_P_SEL2 | REG_EXT_SYNC_SEL2); // bit[3..2]=00, bit[6..5]=11,bit[12]=0 in HAL_EMMFLT_InputMode()
H A DregEMMflt.h271 #define REG_P_SEL2 __BIT5 macro