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Searched refs:REG_MIU_SEL_FIQ0_MASK (Results 1 – 6 of 6) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tsp/
H A DregTSP.h2265 #define REG_MIU_SEL_FIQ0_MASK 0x0300 macro
H A DhalTSP.c8159 …REG16_MSK_W(&_RegCtrl6->CFG6_2E_REG_MIU_PVR_FQ, (REG_MIU_SEL_FIQ0_MASK << u8Shift), (u8MiuSel << (… in HAL_TSP_FQ_MMFI_MIU_Sel()
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsp/
H A DregTSP.h2446 #define REG_MIU_SEL_FIQ0_MASK 0x0300 macro
H A DhalTSP.c8777 …REG16_MSK_W(&_RegCtrl6->CFG6_2E_REG_MIU_PVR_FQ, (REG_MIU_SEL_FIQ0_MASK << u8Shift), (u8MiuSel << (… in HAL_TSP_FQ_MMFI_MIU_Sel()
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsp/
H A DregTSP.h2368 #define REG_MIU_SEL_FIQ0_MASK 0x0300 macro
H A DhalTSP.c8731 …REG16_MSK_W(&_RegCtrl6->CFG6_2E_REG_MIU_PVR_FQ, (REG_MIU_SEL_FIQ0_MASK << u8Shift), (u8MiuSel << (… in HAL_TSP_FQ_MMFI_MIU_Sel()