Home
last modified time | relevance | path

Searched refs:REG_MIU1_DDR_STATUS (Results 1 – 18 of 18) sorted by relevance

/utopia/UTPA2-700.0.x/modules/miu/hal/M7621/miu/
H A DregMIU.h187 #define REG_MIU1_DDR_STATUS (MIU1_ARB_REG_BASE+0x66) macro
H A DhalMIU.c2201 u32Reg = REG_MIU1_DDR_STATUS; in HAL_MIU_GetDramType()
/utopia/UTPA2-700.0.x/modules/miu/hal/mustang/miu/
H A DregMIU.h187 #define REG_MIU1_DDR_STATUS (MIU1_ARB_REG_BASE+0x66) macro
H A DhalMIU.c2308 u32Reg = REG_MIU1_DDR_STATUS; in HAL_MIU_GetDramType()
/utopia/UTPA2-700.0.x/modules/miu/hal/maxim/miu/
H A DregMIU.h187 #define REG_MIU1_DDR_STATUS (MIU1_ARB_REG_BASE+0x66) macro
H A DhalMIU.c2195 u32Reg = REG_MIU1_DDR_STATUS; in HAL_MIU_GetDramType()
/utopia/UTPA2-700.0.x/modules/miu/hal/k6lite/miu/
H A DregMIU.h197 #define REG_MIU1_DDR_STATUS (MIU1_ARB_REG_BASE+0x66) macro
H A DhalMIU.c2340 u32Reg = REG_MIU1_DDR_STATUS; in HAL_MIU_GetDramType()
/utopia/UTPA2-700.0.x/modules/miu/hal/k6/miu/
H A DregMIU.h197 #define REG_MIU1_DDR_STATUS (MIU1_ARB_REG_BASE+0x66) macro
H A DhalMIU.c2341 u32Reg = REG_MIU1_DDR_STATUS; in HAL_MIU_GetDramType()
/utopia/UTPA2-700.0.x/modules/miu/hal/k7u/miu/
H A DregMIU.h197 #define REG_MIU1_DDR_STATUS (MIU1_ARB_REG_BASE+0x66) macro
H A DhalMIU.c2341 u32Reg = REG_MIU1_DDR_STATUS; in HAL_MIU_GetDramType()
/utopia/UTPA2-700.0.x/modules/miu/hal/kano/miu/
H A DregMIU.h215 #define REG_MIU1_DDR_STATUS (MIU1_ARB_REG_BASE+0x66) macro
H A DhalMIU.c2341 u32Reg = REG_MIU1_DDR_STATUS; in HAL_MIU_GetDramType()
/utopia/UTPA2-700.0.x/modules/miu/hal/M7821/miu/
H A DregMIU.h211 #define REG_MIU1_DDR_STATUS (MIU1_ARB_REG_BASE+0x66) macro
H A DhalMIU.c2635 u32Reg = REG_MIU1_DDR_STATUS; in HAL_MIU_GetDramType()
/utopia/UTPA2-700.0.x/modules/miu/hal/maserati/miu/
H A DregMIU.h211 #define REG_MIU1_DDR_STATUS (MIU1_ARB_REG_BASE+0x66) macro
H A DhalMIU.c2629 u32Reg = REG_MIU1_DDR_STATUS; in HAL_MIU_GetDramType()