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Searched refs:REG_MIU1_BASE (Results 1 – 25 of 60) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dmhal_xc_chip_config.h387 #define REG_MIU1_BASE 0x100600 macro
656 #define MIU1_G0_REQUEST_MASK (REG_MIU1_BASE + 0x46)
657 #define MIU1_G1_REQUEST_MASK (REG_MIU1_BASE + 0x66)
658 #define MIU1_G2_REQUEST_MASK (REG_MIU1_BASE + 0x86)
659 #define MIU1_G3_REQUEST_MASK (REG_MIU1_BASE + 0xA6)
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dmhal_xc_chip_config.h387 #define REG_MIU1_BASE 0x100600 macro
656 #define MIU1_G0_REQUEST_MASK (REG_MIU1_BASE + 0x46)
657 #define MIU1_G1_REQUEST_MASK (REG_MIU1_BASE + 0x66)
658 #define MIU1_G2_REQUEST_MASK (REG_MIU1_BASE + 0x86)
659 #define MIU1_G3_REQUEST_MASK (REG_MIU1_BASE + 0xA6)
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dmhal_xc_chip_config.h478 #define REG_MIU1_BASE 0x100600UL macro
935 #define MIU1_G0_REQUEST_MASK (REG_MIU1_BASE + 0x46)
936 #define MIU1_G1_REQUEST_MASK (REG_MIU1_BASE + 0x66)
937 #define MIU1_G2_REQUEST_MASK (REG_MIU1_BASE + 0x86)
938 #define MIU1_G3_REQUEST_MASK (REG_MIU1_BASE + 0xA6)
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dmhal_xc_chip_config.h476 #define REG_MIU1_BASE 0x100600UL macro
917 #define MIU1_G0_REQUEST_MASK (REG_MIU1_BASE + 0x46)
918 #define MIU1_G1_REQUEST_MASK (REG_MIU1_BASE + 0x66)
919 #define MIU1_G2_REQUEST_MASK (REG_MIU1_BASE + 0x86)
920 #define MIU1_G3_REQUEST_MASK (REG_MIU1_BASE + 0xA6)
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dmhal_xc_chip_config.h496 #define REG_MIU1_BASE 0x100600 macro
952 #define MIU1_G0_REQUEST_MASK (REG_MIU1_BASE + 0x46)
953 #define MIU1_G1_REQUEST_MASK (REG_MIU1_BASE + 0x66)
954 #define MIU1_G2_REQUEST_MASK (REG_MIU1_BASE + 0x86)
955 #define MIU1_G3_REQUEST_MASK (REG_MIU1_BASE + 0xA6)
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dmhal_xc_chip_config.h502 #define REG_MIU1_BASE 0x100600 macro
958 #define MIU1_G0_REQUEST_MASK (REG_MIU1_BASE + 0x46)
959 #define MIU1_G1_REQUEST_MASK (REG_MIU1_BASE + 0x66)
960 #define MIU1_G2_REQUEST_MASK (REG_MIU1_BASE + 0x86)
961 #define MIU1_G3_REQUEST_MASK (REG_MIU1_BASE + 0xA6)
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dmhal_xc_chip_config.h502 #define REG_MIU1_BASE 0x100600 macro
968 #define MIU1_G0_REQUEST_MASK (REG_MIU1_BASE + 0x46)
969 #define MIU1_G1_REQUEST_MASK (REG_MIU1_BASE + 0x66)
970 #define MIU1_G2_REQUEST_MASK (REG_MIU1_BASE + 0x86)
971 #define MIU1_G3_REQUEST_MASK (REG_MIU1_BASE + 0xA6)
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dmhal_xc_chip_config.h504 #define REG_MIU1_BASE 0x100600 macro
962 #define MIU1_G0_REQUEST_MASK (REG_MIU1_BASE + 0x46)
963 #define MIU1_G1_REQUEST_MASK (REG_MIU1_BASE + 0x66)
964 #define MIU1_G2_REQUEST_MASK (REG_MIU1_BASE + 0x86)
965 #define MIU1_G3_REQUEST_MASK (REG_MIU1_BASE + 0xA6)
H A Dmhal_xc_chip_config.h.0503 #define REG_MIU1_BASE 0x100600
961 #define MIU1_G0_REQUEST_MASK (REG_MIU1_BASE + 0x46)
962 #define MIU1_G1_REQUEST_MASK (REG_MIU1_BASE + 0x66)
963 #define MIU1_G2_REQUEST_MASK (REG_MIU1_BASE + 0x86)
964 #define MIU1_G3_REQUEST_MASK (REG_MIU1_BASE + 0xA6)
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dmhal_xc_chip_config.h459 #define REG_MIU1_BASE 0x100600UL macro
982 #define MIU1_G0_REQUEST_MASK (REG_MIU1_BASE + 0x46)
983 #define MIU1_G1_REQUEST_MASK (REG_MIU1_BASE + 0x66)
984 #define MIU1_G2_REQUEST_MASK (REG_MIU1_BASE + 0x86)
985 #define MIU1_G3_REQUEST_MASK (REG_MIU1_BASE + 0xA6)
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dmhal_xc_chip_config.h548 #define REG_MIU1_BASE 0x100600UL macro
1098 #define MIU1_G0_REQUEST_MASK (REG_MIU1_BASE + 0x46)
1099 #define MIU1_G1_REQUEST_MASK (REG_MIU1_BASE + 0x66)
1100 #define MIU1_G2_REQUEST_MASK (REG_MIU1_BASE + 0x86)
1101 #define MIU1_G3_REQUEST_MASK (REG_MIU1_BASE + 0xA6)
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dmhal_xc_chip_config.h516 #define REG_MIU1_BASE 0x100600UL macro
1053 #define MIU1_G0_REQUEST_MASK (REG_MIU1_BASE + 0x46)
1054 #define MIU1_G1_REQUEST_MASK (REG_MIU1_BASE + 0x66)
1055 #define MIU1_G2_REQUEST_MASK (REG_MIU1_BASE + 0x86)
1056 #define MIU1_G3_REQUEST_MASK (REG_MIU1_BASE + 0xA6)
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dmhal_xc_chip_config.h561 #define REG_MIU1_BASE 0x100600UL macro
1110 #define MIU1_G0_REQUEST_MASK (REG_MIU1_BASE + 0x46)
1111 #define MIU1_G1_REQUEST_MASK (REG_MIU1_BASE + 0x66)
1112 #define MIU1_G2_REQUEST_MASK (REG_MIU1_BASE + 0x86)
1113 #define MIU1_G3_REQUEST_MASK (REG_MIU1_BASE + 0xA6)
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dmhal_xc_chip_config.h503 #define REG_MIU1_BASE 0x100600UL macro
1047 #define MIU1_G0_REQUEST_MASK (REG_MIU1_BASE + 0x46)
1048 #define MIU1_G1_REQUEST_MASK (REG_MIU1_BASE + 0x66)
1049 #define MIU1_G2_REQUEST_MASK (REG_MIU1_BASE + 0x86)
1050 #define MIU1_G3_REQUEST_MASK (REG_MIU1_BASE + 0xA6)
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dmhal_xc_chip_config.h566 #define REG_MIU1_BASE 0x100600UL macro
1115 #define MIU1_G0_REQUEST_MASK (REG_MIU1_BASE + 0x46)
1116 #define MIU1_G1_REQUEST_MASK (REG_MIU1_BASE + 0x66)
1117 #define MIU1_G2_REQUEST_MASK (REG_MIU1_BASE + 0x86)
1118 #define MIU1_G3_REQUEST_MASK (REG_MIU1_BASE + 0xA6)
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dmhal_xc_chip_config.h552 #define REG_MIU1_BASE 0x100600UL macro
1102 #define MIU1_G0_REQUEST_MASK (REG_MIU1_BASE + 0x46)
1103 #define MIU1_G1_REQUEST_MASK (REG_MIU1_BASE + 0x66)
1104 #define MIU1_G2_REQUEST_MASK (REG_MIU1_BASE + 0x86)
1105 #define MIU1_G3_REQUEST_MASK (REG_MIU1_BASE + 0xA6)
/utopia/UTPA2-700.0.x/modules/xc/drv/xc/
H A Dmdrv_ld.c691 MDrv_WriteByteMask(REG_MIU1_BASE + 0xF4, 0x00, 0x0C); // IP select in MDrv_XC_LD_Set_MIUSel()
696 MDrv_WriteByteMask(REG_MIU1_BASE + 0xF4, 0x0C, 0x0C); // IP select in MDrv_XC_LD_Set_MIUSel()
702 MDrv_WriteByteMask(REG_MIU1_BASE + 0xF0, 0x00, 0x08); // IP select in MDrv_XC_LD_Set_MIUSel()
707 MDrv_WriteByteMask(REG_MIU1_BASE + 0xF0, 0x08, 0x08); // IP select in MDrv_XC_LD_Set_MIUSel()
713 MDrv_WriteByteMask(REG_MIU1_BASE + 0xF4, 0x00, 0x0C); // IP select in MDrv_XC_LD_Set_MIUSel()
718 MDrv_WriteByteMask(REG_MIU1_BASE + 0xF4, 0x0C, 0x0C); // IP select in MDrv_XC_LD_Set_MIUSel()
724 MDrv_WriteByteMask(REG_MIU1_BASE + 0xF2, 0x00, 0x40); // IP select in MDrv_XC_LD_Set_MIUSel()
729 MDrv_WriteByteMask(REG_MIU1_BASE + 0xF2, 0x40, 0x40); // IP select in MDrv_XC_LD_Set_MIUSel()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_frc.c623 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF0), MIU_SC_G0REQUEST_MASK, MIU_SC_G0REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
624 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF2), MIU_SC_G1REQUEST_MASK, MIU_SC_G1REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
625 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF4), MIU_SC_G2REQUEST_MASK, MIU_SC_G2REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
626 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF6), MIU_SC_G3REQUEST_MASK, MIU_SC_G3REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_frc.c801 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF0), MIU_SC_G0REQUEST_MASK, MIU_SC_G0REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
802 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF2), MIU_SC_G1REQUEST_MASK, MIU_SC_G1REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
803 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF4), MIU_SC_G2REQUEST_MASK, MIU_SC_G2REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
804 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF6), MIU_SC_G3REQUEST_MASK, MIU_SC_G3REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_frc.c784 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF0), MIU_SC_G0REQUEST_MASK, MIU_SC_G0REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
785 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF2), MIU_SC_G1REQUEST_MASK, MIU_SC_G1REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
786 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF4), MIU_SC_G2REQUEST_MASK, MIU_SC_G2REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
787 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF6), MIU_SC_G3REQUEST_MASK, MIU_SC_G3REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_sc.c2317 MDrv_WriteByteMask(REG_MIU1_BASE + 0xF3, 0x07, 0x07); in Hal_SC_set_miusel()
2324 MDrv_WriteByteMask(REG_MIU1_BASE + 0xF3, 0x07, 0x07); in Hal_SC_set_miusel()
2334 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF0), MIU_SC0_G0REQUEST_MASK, MIU_SC0_G0REQUEST_MASK); // MI… in Hal_SC_set_miusel()
2335 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF2), MIU_SC0_G1REQUEST_MASK, MIU_SC0_G1REQUEST_MASK); // MI… in Hal_SC_set_miusel()
2336 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF4), MIU_SC0_G2REQUEST_MASK, MIU_SC0_G2REQUEST_MASK); // MI… in Hal_SC_set_miusel()
2337 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF6), MIU_SC0_G3REQUEST_MASK, MIU_SC0_G3REQUEST_MASK); // MI… in Hal_SC_set_miusel()
2346 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF0), MIU_SC1_G0REQUEST_MASK, MIU_SC1_G0REQUEST_MASK); // MI… in Hal_SC_set_miusel()
2347 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF2), MIU_SC1_G1REQUEST_MASK, MIU_SC1_G1REQUEST_MASK); // MI… in Hal_SC_set_miusel()
2348 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF4), MIU_SC1_G2REQUEST_MASK, MIU_SC1_G2REQUEST_MASK); // MI… in Hal_SC_set_miusel()
2349 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF6), MIU_SC1_G3REQUEST_MASK, MIU_SC1_G3REQUEST_MASK); // MI… in Hal_SC_set_miusel()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_sc.c2230 MDrv_WriteByteMask(REG_MIU1_BASE + 0xF3, 0x07, 0x07); in Hal_SC_set_miusel()
2237 MDrv_WriteByteMask(REG_MIU1_BASE + 0xF3, 0x07, 0x07); in Hal_SC_set_miusel()
2247 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF0), MIU_SC0_G0REQUEST_MASK, MIU_SC0_G0REQUEST_MASK); // MI… in Hal_SC_set_miusel()
2248 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF2), MIU_SC0_G1REQUEST_MASK, MIU_SC0_G1REQUEST_MASK); // MI… in Hal_SC_set_miusel()
2249 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF4), MIU_SC0_G2REQUEST_MASK, MIU_SC0_G2REQUEST_MASK); // MI… in Hal_SC_set_miusel()
2250 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF6), MIU_SC0_G3REQUEST_MASK, MIU_SC0_G3REQUEST_MASK); // MI… in Hal_SC_set_miusel()
2259 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF0), MIU_SC1_G0REQUEST_MASK, MIU_SC1_G0REQUEST_MASK); // MI… in Hal_SC_set_miusel()
2260 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF2), MIU_SC1_G1REQUEST_MASK, MIU_SC1_G1REQUEST_MASK); // MI… in Hal_SC_set_miusel()
2261 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF4), MIU_SC1_G2REQUEST_MASK, MIU_SC1_G2REQUEST_MASK); // MI… in Hal_SC_set_miusel()
2262 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF6), MIU_SC1_G3REQUEST_MASK, MIU_SC1_G3REQUEST_MASK); // MI… in Hal_SC_set_miusel()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_sc.c2327 MDrv_WriteByteMask(REG_MIU1_BASE + 0xF3, 0x07, 0x07); in Hal_SC_set_miusel()
2334 MDrv_WriteByteMask(REG_MIU1_BASE + 0xF3, 0x07, 0x07); in Hal_SC_set_miusel()
2344 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF0), MIU_SC0_G0REQUEST_MASK, MIU_SC0_G0REQUEST_MASK); // MI… in Hal_SC_set_miusel()
2345 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF2), MIU_SC0_G1REQUEST_MASK, MIU_SC0_G1REQUEST_MASK); // MI… in Hal_SC_set_miusel()
2346 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF4), MIU_SC0_G2REQUEST_MASK, MIU_SC0_G2REQUEST_MASK); // MI… in Hal_SC_set_miusel()
2347 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF6), MIU_SC0_G3REQUEST_MASK, MIU_SC0_G3REQUEST_MASK); // MI… in Hal_SC_set_miusel()
2356 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF0), MIU_SC1_G0REQUEST_MASK, MIU_SC1_G0REQUEST_MASK); // MI… in Hal_SC_set_miusel()
2357 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF2), MIU_SC1_G1REQUEST_MASK, MIU_SC1_G1REQUEST_MASK); // MI… in Hal_SC_set_miusel()
2358 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF4), MIU_SC1_G2REQUEST_MASK, MIU_SC1_G2REQUEST_MASK); // MI… in Hal_SC_set_miusel()
2359 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF6), MIU_SC1_G3REQUEST_MASK, MIU_SC1_G3REQUEST_MASK); // MI… in Hal_SC_set_miusel()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_sc.c2528 MDrv_WriteByteMask(REG_MIU1_BASE + 0xF3, 0x07, 0x07); in Hal_SC_set_miusel()
2535 MDrv_WriteByteMask(REG_MIU1_BASE + 0xF3, 0x07, 0x07); in Hal_SC_set_miusel()
2545 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF0), MIU_SC0_G0REQUEST_MASK, MIU_SC0_G0REQUEST_MASK); // MI… in Hal_SC_set_miusel()
2546 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF2), MIU_SC0_G1REQUEST_MASK, MIU_SC0_G1REQUEST_MASK); // MI… in Hal_SC_set_miusel()
2547 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF4), MIU_SC0_G2REQUEST_MASK, MIU_SC0_G2REQUEST_MASK); // MI… in Hal_SC_set_miusel()
2548 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF6), MIU_SC0_G3REQUEST_MASK, MIU_SC0_G3REQUEST_MASK); // MI… in Hal_SC_set_miusel()
2557 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF0), MIU_SC1_G0REQUEST_MASK, MIU_SC1_G0REQUEST_MASK); // MI… in Hal_SC_set_miusel()
2558 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF2), MIU_SC1_G1REQUEST_MASK, MIU_SC1_G1REQUEST_MASK); // MI… in Hal_SC_set_miusel()
2559 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF4), MIU_SC1_G2REQUEST_MASK, MIU_SC1_G2REQUEST_MASK); // MI… in Hal_SC_set_miusel()
2560 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF6), MIU_SC1_G3REQUEST_MASK, MIU_SC1_G3REQUEST_MASK); // MI… in Hal_SC_set_miusel()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_frc.c762 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF0), MIU_SC_G0REQUEST_MASK, MIU_SC_G0REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
763 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF2), MIU_SC_G1REQUEST_MASK, MIU_SC_G1REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
764 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF4), MIU_SC_G2REQUEST_MASK, MIU_SC_G2REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
765 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF6), MIU_SC_G3REQUEST_MASK, MIU_SC_G3REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()

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