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Searched refs:REG_MIPS_C_IRQ_EXP_MASK (Results 1 – 16 of 16) sorted by relevance

/utopia/UTPA2-700.0.x/modules/irq/hal/M7821/irq/
H A DregIRQ.h189 #define REG_MIPS_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + 0x36*2) //[IRQ][HAL][009] Mask b… macro
258 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
284 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
308 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
331 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
355 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
378 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
/utopia/UTPA2-700.0.x/modules/irq/hal/macan/irq/
H A DregIRQ.h189 #define REG_MIPS_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + 0x36*2) macro
258 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
284 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
308 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
331 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
355 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
378 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
/utopia/UTPA2-700.0.x/modules/irq/hal/maserati/irq/
H A DregIRQ.h189 #define REG_MIPS_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + 0x36*2) macro
258 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
284 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
308 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
331 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
355 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
/utopia/UTPA2-700.0.x/modules/irq/hal/manhattan/irq/
H A DregIRQ.h189 #define REG_MIPS_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + 0x36*2) macro
258 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
284 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
308 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
331 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
355 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
/utopia/UTPA2-700.0.x/modules/irq/hal/maxim/irq/
H A DregIRQ.h189 #define REG_MIPS_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + 0x36*2) macro
258 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
284 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
308 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
331 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
355 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
/utopia/UTPA2-700.0.x/modules/irq/hal/M7621/irq/
H A DregIRQ.h189 #define REG_MIPS_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + 0x36*2) //[IRQ][HAL][009] Mask b… macro
258 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
284 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
308 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
331 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
355 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
/utopia/UTPA2-700.0.x/modules/irq/hal/mustang/irq/
H A DregIRQ.h147 #define REG_MIPS_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + 0x56*2) macro
179 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
197 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
213 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
229 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
/utopia/UTPA2-700.0.x/modules/irq/hal/maldives/irq/
H A DregIRQ.h147 #define REG_MIPS_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + 0x56*2) macro
179 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
197 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
213 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
229 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
/utopia/UTPA2-700.0.x/modules/irq/hal/mainz/irq/
H A DregIRQ.h137 #define REG_MIPS_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x0036 << 1)) macro
169 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
/utopia/UTPA2-700.0.x/modules/irq/hal/mooney/irq/
H A DregIRQ.h137 #define REG_MIPS_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x0036 << 1)) macro
169 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
/utopia/UTPA2-700.0.x/modules/irq/hal/messi/irq/
H A DregIRQ.h137 #define REG_MIPS_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x0036 << 1)) macro
169 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
/utopia/UTPA2-700.0.x/modules/irq/hal/kano/irq/
H A DregIRQ.h148 #define REG_MIPS_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x56 << 1)) macro
192 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
/utopia/UTPA2-700.0.x/modules/irq/hal/k7u/irq/
H A DregIRQ.h148 #define REG_MIPS_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x56 << 1)) macro
192 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
/utopia/UTPA2-700.0.x/modules/irq/hal/k6lite/irq/
H A DregIRQ.h148 #define REG_MIPS_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x56 << 1)) macro
192 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
/utopia/UTPA2-700.0.x/modules/irq/hal/curry/irq/
H A DregIRQ.h148 #define REG_MIPS_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x56 << 1)) macro
192 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK
/utopia/UTPA2-700.0.x/modules/irq/hal/k6/irq/
H A DregIRQ.h148 #define REG_MIPS_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x56 << 1)) macro
192 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK