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Searched refs:REG_MIPS_C_IRQ_EXP_FINAL_STATUS (Results 1 – 16 of 16) sorted by relevance

/utopia/UTPA2-700.0.x/modules/irq/hal/M7821/irq/
H A DregIRQ.h190 #define REG_MIPS_C_IRQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + 0x3E*2) //[IRQ][HAL][010] Status… macro
259 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
285 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
309 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
332 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
356 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
379 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
/utopia/UTPA2-700.0.x/modules/irq/hal/macan/irq/
H A DregIRQ.h190 #define REG_MIPS_C_IRQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + 0x3E*2) macro
259 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
285 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
309 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
332 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
356 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
379 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
/utopia/UTPA2-700.0.x/modules/irq/hal/maserati/irq/
H A DregIRQ.h190 #define REG_MIPS_C_IRQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + 0x3E*2) macro
259 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
285 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
309 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
332 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
356 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
/utopia/UTPA2-700.0.x/modules/irq/hal/manhattan/irq/
H A DregIRQ.h190 #define REG_MIPS_C_IRQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + 0x3E*2) macro
259 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
285 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
309 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
332 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
356 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
/utopia/UTPA2-700.0.x/modules/irq/hal/maxim/irq/
H A DregIRQ.h190 #define REG_MIPS_C_IRQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + 0x3E*2) macro
259 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
285 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
309 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
332 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
356 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
/utopia/UTPA2-700.0.x/modules/irq/hal/M7621/irq/
H A DregIRQ.h190 #define REG_MIPS_C_IRQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + 0x3E*2) //[IRQ][HAL][010] Status… macro
259 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
285 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
309 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
332 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
356 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
/utopia/UTPA2-700.0.x/modules/irq/hal/mustang/irq/
H A DregIRQ.h148 #define REG_MIPS_C_IRQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + 0x5E*2) macro
180 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
198 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
214 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
230 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
/utopia/UTPA2-700.0.x/modules/irq/hal/maldives/irq/
H A DregIRQ.h148 #define REG_MIPS_C_IRQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + 0x5E*2) macro
180 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
198 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
214 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
230 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
/utopia/UTPA2-700.0.x/modules/irq/hal/mainz/irq/
H A DregIRQ.h138 #define REG_MIPS_C_IRQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x003E << 1)) macro
170 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
/utopia/UTPA2-700.0.x/modules/irq/hal/mooney/irq/
H A DregIRQ.h138 #define REG_MIPS_C_IRQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x003E << 1)) macro
170 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
/utopia/UTPA2-700.0.x/modules/irq/hal/messi/irq/
H A DregIRQ.h138 #define REG_MIPS_C_IRQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x003E << 1)) macro
170 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
/utopia/UTPA2-700.0.x/modules/irq/hal/kano/irq/
H A DregIRQ.h149 #define REG_MIPS_C_IRQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x5e << 1)) macro
193 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
/utopia/UTPA2-700.0.x/modules/irq/hal/k7u/irq/
H A DregIRQ.h149 #define REG_MIPS_C_IRQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x5e << 1)) macro
193 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
/utopia/UTPA2-700.0.x/modules/irq/hal/k6lite/irq/
H A DregIRQ.h149 #define REG_MIPS_C_IRQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x5e << 1)) macro
193 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
/utopia/UTPA2-700.0.x/modules/irq/hal/curry/irq/
H A DregIRQ.h149 #define REG_MIPS_C_IRQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x5e << 1)) macro
193 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS
/utopia/UTPA2-700.0.x/modules/irq/hal/k6/irq/
H A DregIRQ.h149 #define REG_MIPS_C_IRQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x5e << 1)) macro
193 #define REG_C_IRQ_EXP_FINAL_STATUS REG_MIPS_C_IRQ_EXP_FINAL_STATUS