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Searched refs:REG_MIPS_C_FIQ_EXP_MASK (Results 1 – 16 of 16) sorted by relevance

/utopia/UTPA2-700.0.x/modules/irq/hal/M7821/irq/
H A DregIRQ.h181 #define REG_MIPS_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + 0x26*2) //[IRQ][HAL][004] Mask b… macro
250 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
276 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
300 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
323 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
347 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
370 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
/utopia/UTPA2-700.0.x/modules/irq/hal/macan/irq/
H A DregIRQ.h181 #define REG_MIPS_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + 0x26*2) macro
250 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
276 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
300 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
323 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
347 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
370 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
/utopia/UTPA2-700.0.x/modules/irq/hal/maserati/irq/
H A DregIRQ.h181 #define REG_MIPS_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + 0x26*2) macro
250 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
276 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
300 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
323 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
347 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
/utopia/UTPA2-700.0.x/modules/irq/hal/manhattan/irq/
H A DregIRQ.h181 #define REG_MIPS_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + 0x26*2) macro
250 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
276 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
300 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
323 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
347 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
/utopia/UTPA2-700.0.x/modules/irq/hal/maxim/irq/
H A DregIRQ.h181 #define REG_MIPS_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + 0x26*2) macro
250 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
276 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
300 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
323 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
347 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
/utopia/UTPA2-700.0.x/modules/irq/hal/M7621/irq/
H A DregIRQ.h181 #define REG_MIPS_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + 0x26*2) //[IRQ][HAL][004] Mask b… macro
250 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
276 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
300 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
323 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
347 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
/utopia/UTPA2-700.0.x/modules/irq/hal/mustang/irq/
H A DregIRQ.h143 #define REG_MIPS_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + 0x46*2) macro
175 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
193 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
209 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
225 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
/utopia/UTPA2-700.0.x/modules/irq/hal/maldives/irq/
H A DregIRQ.h143 #define REG_MIPS_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + 0x46*2) macro
175 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
193 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
209 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
225 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
/utopia/UTPA2-700.0.x/modules/irq/hal/mainz/irq/
H A DregIRQ.h133 #define REG_MIPS_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x0026 << 1)) macro
165 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
/utopia/UTPA2-700.0.x/modules/irq/hal/mooney/irq/
H A DregIRQ.h133 #define REG_MIPS_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x0026 << 1)) macro
165 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
/utopia/UTPA2-700.0.x/modules/irq/hal/messi/irq/
H A DregIRQ.h133 #define REG_MIPS_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x0026 << 1)) macro
165 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
/utopia/UTPA2-700.0.x/modules/irq/hal/kano/irq/
H A DregIRQ.h141 #define REG_MIPS_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x46 << 1)) macro
184 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
/utopia/UTPA2-700.0.x/modules/irq/hal/k7u/irq/
H A DregIRQ.h141 #define REG_MIPS_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x46 << 1)) macro
184 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
/utopia/UTPA2-700.0.x/modules/irq/hal/k6lite/irq/
H A DregIRQ.h141 #define REG_MIPS_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x46 << 1)) macro
184 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
/utopia/UTPA2-700.0.x/modules/irq/hal/curry/irq/
H A DregIRQ.h141 #define REG_MIPS_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x46 << 1)) macro
184 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK
/utopia/UTPA2-700.0.x/modules/irq/hal/k6/irq/
H A DregIRQ.h141 #define REG_MIPS_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x46 << 1)) macro
184 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK