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Searched refs:REG_MIPS_C_FIQ_EXP_FINAL_STATUS (Results 1 – 16 of 16) sorted by relevance

/utopia/UTPA2-700.0.x/modules/irq/hal/M7821/irq/
H A DregIRQ.h183 #define REG_MIPS_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + 0x2E*2) //[IRQ][HAL][006] Status… macro
252 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
278 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
302 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
325 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
349 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
372 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
/utopia/UTPA2-700.0.x/modules/irq/hal/macan/irq/
H A DregIRQ.h183 #define REG_MIPS_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + 0x2E*2) macro
252 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
278 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
302 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
325 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
349 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
372 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
/utopia/UTPA2-700.0.x/modules/irq/hal/maserati/irq/
H A DregIRQ.h183 #define REG_MIPS_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + 0x2E*2) macro
252 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
278 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
302 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
325 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
349 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
/utopia/UTPA2-700.0.x/modules/irq/hal/manhattan/irq/
H A DregIRQ.h183 #define REG_MIPS_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + 0x2E*2) macro
252 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
278 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
302 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
325 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
349 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
/utopia/UTPA2-700.0.x/modules/irq/hal/maxim/irq/
H A DregIRQ.h183 #define REG_MIPS_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + 0x2E*2) macro
252 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
278 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
302 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
325 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
349 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
/utopia/UTPA2-700.0.x/modules/irq/hal/M7621/irq/
H A DregIRQ.h183 #define REG_MIPS_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + 0x2E*2) //[IRQ][HAL][006] Status… macro
252 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
278 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
302 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
325 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
349 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
/utopia/UTPA2-700.0.x/modules/irq/hal/mustang/irq/
H A DregIRQ.h145 #define REG_MIPS_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + 0x4E*2) macro
177 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
195 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
211 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
227 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
/utopia/UTPA2-700.0.x/modules/irq/hal/maldives/irq/
H A DregIRQ.h145 #define REG_MIPS_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + 0x4E*2) macro
177 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
195 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
211 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
227 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
/utopia/UTPA2-700.0.x/modules/irq/hal/mainz/irq/
H A DregIRQ.h135 #define REG_MIPS_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x002E << 1)) macro
167 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
/utopia/UTPA2-700.0.x/modules/irq/hal/mooney/irq/
H A DregIRQ.h135 #define REG_MIPS_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x002E << 1)) macro
167 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
/utopia/UTPA2-700.0.x/modules/irq/hal/messi/irq/
H A DregIRQ.h135 #define REG_MIPS_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x002E << 1)) macro
167 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
/utopia/UTPA2-700.0.x/modules/irq/hal/kano/irq/
H A DregIRQ.h143 #define REG_MIPS_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x4e << 1)) macro
186 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
/utopia/UTPA2-700.0.x/modules/irq/hal/k7u/irq/
H A DregIRQ.h143 #define REG_MIPS_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x4e << 1)) macro
186 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
/utopia/UTPA2-700.0.x/modules/irq/hal/k6lite/irq/
H A DregIRQ.h143 #define REG_MIPS_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x4e << 1)) macro
186 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
/utopia/UTPA2-700.0.x/modules/irq/hal/curry/irq/
H A DregIRQ.h143 #define REG_MIPS_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x4e << 1)) macro
186 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS
/utopia/UTPA2-700.0.x/modules/irq/hal/k6/irq/
H A DregIRQ.h143 #define REG_MIPS_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x4e << 1)) macro
186 #define REG_C_FIQ_EXP_FINAL_STATUS REG_MIPS_C_FIQ_EXP_FINAL_STATUS