Home
last modified time | relevance | path

Searched refs:REG_IRQ_MASK_L (Results 1 – 25 of 28) sorted by relevance

12

/utopia/UTPA2-700.0.x/mxlib/hal/k7u/
H A DhalCHIP.c507 IRQ_REG(REG_IRQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
523 IRQ_REG(REG_IRQ_MASK_L) &= ~(0x01 << (u8VectorIndex - E_IRQL_START)); in CHIP_EnableIRQ()
586 IRQ_REG(REG_IRQ_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
602 IRQ_REG(REG_IRQ_MASK_L) |= (0x01 << (u8VectorIndex - E_IRQL_START)); in CHIP_DisableIRQ()
1643 IRQ_REG(REG_IRQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
1659 IRQ_REG(REG_IRQ_MASK_L) &= ~(0x01 << (u8VectorIndex - E_IRQL_START)); in CHIP_EnableIRQ()
1722 IRQ_REG(REG_IRQ_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
1738 IRQ_REG(REG_IRQ_MASK_L) |= (0x01 << (u8VectorIndex - E_IRQL_START)); in CHIP_DisableIRQ()
H A DregCHIP.h128 #define REG_IRQ_MASK_L 0x0034 macro
172 #define REG_IRQ_MASK_L (REG_INT_BASE_ADDR + 0x0014) macro
/utopia/UTPA2-700.0.x/mxlib/hal/k6lite/
H A DhalCHIP.c507 IRQ_REG(REG_IRQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
523 IRQ_REG(REG_IRQ_MASK_L) &= ~(0x01 << (u8VectorIndex - E_IRQL_START)); in CHIP_EnableIRQ()
586 IRQ_REG(REG_IRQ_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
602 IRQ_REG(REG_IRQ_MASK_L) |= (0x01 << (u8VectorIndex - E_IRQL_START)); in CHIP_DisableIRQ()
1643 IRQ_REG(REG_IRQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
1659 IRQ_REG(REG_IRQ_MASK_L) &= ~(0x01 << (u8VectorIndex - E_IRQL_START)); in CHIP_EnableIRQ()
1722 IRQ_REG(REG_IRQ_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
1738 IRQ_REG(REG_IRQ_MASK_L) |= (0x01 << (u8VectorIndex - E_IRQL_START)); in CHIP_DisableIRQ()
H A DregCHIP.h128 #define REG_IRQ_MASK_L 0x0034 macro
172 #define REG_IRQ_MASK_L (REG_INT_BASE_ADDR + 0x0014) macro
/utopia/UTPA2-700.0.x/mxlib/hal/curry/
H A DhalCHIP.c507 IRQ_REG(REG_IRQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
523 IRQ_REG(REG_IRQ_MASK_L) &= ~(0x01 << (u8VectorIndex - E_IRQL_START)); in CHIP_EnableIRQ()
586 IRQ_REG(REG_IRQ_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
602 IRQ_REG(REG_IRQ_MASK_L) |= (0x01 << (u8VectorIndex - E_IRQL_START)); in CHIP_DisableIRQ()
1630 IRQ_REG(REG_IRQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
1646 IRQ_REG(REG_IRQ_MASK_L) &= ~(0x01 << (u8VectorIndex - E_IRQL_START)); in CHIP_EnableIRQ()
1709 IRQ_REG(REG_IRQ_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
1725 IRQ_REG(REG_IRQ_MASK_L) |= (0x01 << (u8VectorIndex - E_IRQL_START)); in CHIP_DisableIRQ()
H A DregCHIP.h128 #define REG_IRQ_MASK_L 0x0034 macro
172 #define REG_IRQ_MASK_L (REG_INT_BASE_ADDR + 0x0014) macro
/utopia/UTPA2-700.0.x/mxlib/hal/kano/
H A DhalCHIP.c507 IRQ_REG(REG_IRQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
523 IRQ_REG(REG_IRQ_MASK_L) &= ~(0x01 << (u8VectorIndex - E_IRQL_START)); in CHIP_EnableIRQ()
586 IRQ_REG(REG_IRQ_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
602 IRQ_REG(REG_IRQ_MASK_L) |= (0x01 << (u8VectorIndex - E_IRQL_START)); in CHIP_DisableIRQ()
1643 IRQ_REG(REG_IRQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
1659 IRQ_REG(REG_IRQ_MASK_L) &= ~(0x01 << (u8VectorIndex - E_IRQL_START)); in CHIP_EnableIRQ()
1722 IRQ_REG(REG_IRQ_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
1738 IRQ_REG(REG_IRQ_MASK_L) |= (0x01 << (u8VectorIndex - E_IRQL_START)); in CHIP_DisableIRQ()
H A DregCHIP.h128 #define REG_IRQ_MASK_L 0x0034 macro
172 #define REG_IRQ_MASK_L (REG_INT_BASE_ADDR + 0x0014) macro
/utopia/UTPA2-700.0.x/mxlib/hal/k6/
H A DhalCHIP.c507 IRQ_REG(REG_IRQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
523 IRQ_REG(REG_IRQ_MASK_L) &= ~(0x01 << (u8VectorIndex - E_IRQL_START)); in CHIP_EnableIRQ()
586 IRQ_REG(REG_IRQ_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
602 IRQ_REG(REG_IRQ_MASK_L) |= (0x01 << (u8VectorIndex - E_IRQL_START)); in CHIP_DisableIRQ()
1643 IRQ_REG(REG_IRQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
1659 IRQ_REG(REG_IRQ_MASK_L) &= ~(0x01 << (u8VectorIndex - E_IRQL_START)); in CHIP_EnableIRQ()
1722 IRQ_REG(REG_IRQ_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
1738 IRQ_REG(REG_IRQ_MASK_L) |= (0x01 << (u8VectorIndex - E_IRQL_START)); in CHIP_DisableIRQ()
H A DregCHIP.h128 #define REG_IRQ_MASK_L 0x0034 macro
172 #define REG_IRQ_MASK_L (REG_INT_BASE_ADDR + 0x0014) macro
/utopia/UTPA2-700.0.x/mxlib/hal/M7821/
H A DhalCHIP.c439 IRQ_REG(REG_IRQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
450 IRQ_REG(REG_IRQ_MASK_L) &= ~(0x1 << (u8VectorIndex-E_IRQL_START) ); in CHIP_EnableIRQ()
498 IRQ_REG(REG_IRQ_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
509 IRQ_REG(REG_IRQ_MASK_L) |= (0x1 << (u8VectorIndex-E_IRQL_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h147 #define REG_IRQ_MASK_L 0x0034 macro
174 #define REG_IRQ_MASK_L 0x0034 macro
/utopia/UTPA2-700.0.x/mxlib/hal/maxim/
H A DhalCHIP.c439 IRQ_REG(REG_IRQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
450 IRQ_REG(REG_IRQ_MASK_L) &= ~(0x1 << (u8VectorIndex-E_IRQL_START) ); in CHIP_EnableIRQ()
498 IRQ_REG(REG_IRQ_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
509 IRQ_REG(REG_IRQ_MASK_L) |= (0x1 << (u8VectorIndex-E_IRQL_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h147 #define REG_IRQ_MASK_L 0x0034 macro
172 #define REG_IRQ_MASK_L 0x0034 macro
/utopia/UTPA2-700.0.x/mxlib/hal/marcus/
H A DhalCHIP.c439 IRQ_REG(REG_IRQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
450 IRQ_REG(REG_IRQ_MASK_L) &= ~(0x1 << (u8VectorIndex-E_IRQL_START) ); in CHIP_EnableIRQ()
498 IRQ_REG(REG_IRQ_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
509 IRQ_REG(REG_IRQ_MASK_L) |= (0x1 << (u8VectorIndex-E_IRQL_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h147 #define REG_IRQ_MASK_L 0x0034 macro
172 #define REG_IRQ_MASK_L 0x0034 macro
/utopia/UTPA2-700.0.x/mxlib/hal/mainz/
H A DhalCHIP.c422 IRQ_REG(REG_IRQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
433 IRQ_REG(REG_IRQ_MASK_L) &= ~(0x01 << (u8VectorIndex - E_IRQL_START)); in CHIP_EnableIRQ()
480 IRQ_REG(REG_IRQ_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
491 IRQ_REG(REG_IRQ_MASK_L) |= (0x01 << (u8VectorIndex - E_IRQL_START)); in CHIP_DisableIRQ()
/utopia/UTPA2-700.0.x/mxlib/hal/maserati/
H A DhalCHIP.c439 IRQ_REG(REG_IRQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
450 IRQ_REG(REG_IRQ_MASK_L) &= ~(0x1 << (u8VectorIndex-E_IRQL_START) ); in CHIP_EnableIRQ()
498 IRQ_REG(REG_IRQ_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
509 IRQ_REG(REG_IRQ_MASK_L) |= (0x1 << (u8VectorIndex-E_IRQL_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h147 #define REG_IRQ_MASK_L 0x0034 macro
172 #define REG_IRQ_MASK_L 0x0034 macro
/utopia/UTPA2-700.0.x/mxlib/hal/manhattan/
H A DhalCHIP.c439 IRQ_REG(REG_IRQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
450 IRQ_REG(REG_IRQ_MASK_L) &= ~(0x1 << (u8VectorIndex-E_IRQL_START) ); in CHIP_EnableIRQ()
498 IRQ_REG(REG_IRQ_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
509 IRQ_REG(REG_IRQ_MASK_L) |= (0x1 << (u8VectorIndex-E_IRQL_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h147 #define REG_IRQ_MASK_L 0x0034 macro
172 #define REG_IRQ_MASK_L 0x0034 macro
/utopia/UTPA2-700.0.x/mxlib/hal/mustang/
H A DhalCHIP.c422 IRQ_REG(REG_IRQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
433 IRQ_REG(REG_IRQ_MASK_L) &= ~(0x01 << (u8VectorIndex - E_IRQL_START)); in CHIP_EnableIRQ()
480 IRQ_REG(REG_IRQ_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
491 IRQ_REG(REG_IRQ_MASK_L) |= (0x01 << (u8VectorIndex - E_IRQL_START)); in CHIP_DisableIRQ()
/utopia/UTPA2-700.0.x/mxlib/hal/messi/
H A DhalCHIP.c422 IRQ_REG(REG_IRQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
433 IRQ_REG(REG_IRQ_MASK_L) &= ~(0x01 << (u8VectorIndex - E_IRQL_START)); in CHIP_EnableIRQ()
480 IRQ_REG(REG_IRQ_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
491 IRQ_REG(REG_IRQ_MASK_L) |= (0x01 << (u8VectorIndex - E_IRQL_START)); in CHIP_DisableIRQ()
/utopia/UTPA2-700.0.x/mxlib/hal/M7621/
H A DhalCHIP.c439 IRQ_REG(REG_IRQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
450 IRQ_REG(REG_IRQ_MASK_L) &= ~(0x1 << (u8VectorIndex-E_IRQL_START) ); in CHIP_EnableIRQ()
498 IRQ_REG(REG_IRQ_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
509 IRQ_REG(REG_IRQ_MASK_L) |= (0x1 << (u8VectorIndex-E_IRQL_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h147 #define REG_IRQ_MASK_L 0x0034 macro
174 #define REG_IRQ_MASK_L 0x0034 macro

12