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Searched refs:REG_IRQEXP_MASK_L (Results 1 – 25 of 28) sorted by relevance

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/utopia/UTPA2-700.0.x/mxlib/hal/k7u/
H A DhalCHIP.c509 IRQ_REG(REG_IRQEXP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
531 IRQ_REG(REG_IRQEXP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_IRQEXPL_START)); in CHIP_EnableIRQ()
588 IRQ_REG(REG_IRQEXP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
610 IRQ_REG(REG_IRQEXP_MASK_L) |= (0x01 << (u8VectorIndex - E_IRQEXPL_START)); in CHIP_DisableIRQ()
1645 IRQ_REG(REG_IRQEXP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
1667 IRQ_REG(REG_IRQEXP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_IRQEXPL_START)); in CHIP_EnableIRQ()
1724 IRQ_REG(REG_IRQEXP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
1746 IRQ_REG(REG_IRQEXP_MASK_L) |= (0x01 << (u8VectorIndex - E_IRQEXPL_START)); in CHIP_DisableIRQ()
H A DregCHIP.h130 #define REG_IRQEXP_MASK_L 0x0036 macro
174 #define REG_IRQEXP_MASK_L (REG_INT_BASE_ADDR + 0x0016) macro
/utopia/UTPA2-700.0.x/mxlib/hal/k6lite/
H A DhalCHIP.c509 IRQ_REG(REG_IRQEXP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
531 IRQ_REG(REG_IRQEXP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_IRQEXPL_START)); in CHIP_EnableIRQ()
588 IRQ_REG(REG_IRQEXP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
610 IRQ_REG(REG_IRQEXP_MASK_L) |= (0x01 << (u8VectorIndex - E_IRQEXPL_START)); in CHIP_DisableIRQ()
1645 IRQ_REG(REG_IRQEXP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
1667 IRQ_REG(REG_IRQEXP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_IRQEXPL_START)); in CHIP_EnableIRQ()
1724 IRQ_REG(REG_IRQEXP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
1746 IRQ_REG(REG_IRQEXP_MASK_L) |= (0x01 << (u8VectorIndex - E_IRQEXPL_START)); in CHIP_DisableIRQ()
H A DregCHIP.h130 #define REG_IRQEXP_MASK_L 0x0036 macro
174 #define REG_IRQEXP_MASK_L (REG_INT_BASE_ADDR + 0x0016) macro
/utopia/UTPA2-700.0.x/mxlib/hal/curry/
H A DhalCHIP.c509 IRQ_REG(REG_IRQEXP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
531 IRQ_REG(REG_IRQEXP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_IRQEXPL_START)); in CHIP_EnableIRQ()
588 IRQ_REG(REG_IRQEXP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
610 IRQ_REG(REG_IRQEXP_MASK_L) |= (0x01 << (u8VectorIndex - E_IRQEXPL_START)); in CHIP_DisableIRQ()
1632 IRQ_REG(REG_IRQEXP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
1654 IRQ_REG(REG_IRQEXP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_IRQEXPL_START)); in CHIP_EnableIRQ()
1711 IRQ_REG(REG_IRQEXP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
1733 IRQ_REG(REG_IRQEXP_MASK_L) |= (0x01 << (u8VectorIndex - E_IRQEXPL_START)); in CHIP_DisableIRQ()
H A DregCHIP.h130 #define REG_IRQEXP_MASK_L 0x0036 macro
174 #define REG_IRQEXP_MASK_L (REG_INT_BASE_ADDR + 0x0016) macro
/utopia/UTPA2-700.0.x/mxlib/hal/kano/
H A DhalCHIP.c509 IRQ_REG(REG_IRQEXP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
531 IRQ_REG(REG_IRQEXP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_IRQEXPL_START)); in CHIP_EnableIRQ()
588 IRQ_REG(REG_IRQEXP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
610 IRQ_REG(REG_IRQEXP_MASK_L) |= (0x01 << (u8VectorIndex - E_IRQEXPL_START)); in CHIP_DisableIRQ()
1645 IRQ_REG(REG_IRQEXP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
1667 IRQ_REG(REG_IRQEXP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_IRQEXPL_START)); in CHIP_EnableIRQ()
1724 IRQ_REG(REG_IRQEXP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
1746 IRQ_REG(REG_IRQEXP_MASK_L) |= (0x01 << (u8VectorIndex - E_IRQEXPL_START)); in CHIP_DisableIRQ()
H A DregCHIP.h130 #define REG_IRQEXP_MASK_L 0x0036 macro
174 #define REG_IRQEXP_MASK_L (REG_INT_BASE_ADDR + 0x0016) macro
/utopia/UTPA2-700.0.x/mxlib/hal/k6/
H A DhalCHIP.c509 IRQ_REG(REG_IRQEXP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
531 IRQ_REG(REG_IRQEXP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_IRQEXPL_START)); in CHIP_EnableIRQ()
588 IRQ_REG(REG_IRQEXP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
610 IRQ_REG(REG_IRQEXP_MASK_L) |= (0x01 << (u8VectorIndex - E_IRQEXPL_START)); in CHIP_DisableIRQ()
1645 IRQ_REG(REG_IRQEXP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
1667 IRQ_REG(REG_IRQEXP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_IRQEXPL_START)); in CHIP_EnableIRQ()
1724 IRQ_REG(REG_IRQEXP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
1746 IRQ_REG(REG_IRQEXP_MASK_L) |= (0x01 << (u8VectorIndex - E_IRQEXPL_START)); in CHIP_DisableIRQ()
H A DregCHIP.h130 #define REG_IRQEXP_MASK_L 0x0036 macro
174 #define REG_IRQEXP_MASK_L (REG_INT_BASE_ADDR + 0x0016) macro
/utopia/UTPA2-700.0.x/mxlib/hal/M7821/
H A DhalCHIP.c441 IRQ_REG(REG_IRQEXP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
458 IRQ_REG(REG_IRQEXP_MASK_L) &= ~(0x1 << (u8VectorIndex-E_IRQEXPL_START) ); in CHIP_EnableIRQ()
500 IRQ_REG(REG_IRQEXP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
517 IRQ_REG(REG_IRQEXP_MASK_L) |= (0x1 << (u8VectorIndex-E_IRQEXPL_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h149 #define REG_IRQEXP_MASK_L 0x0036 macro
176 #define REG_IRQEXP_MASK_L 0x0036 macro
/utopia/UTPA2-700.0.x/mxlib/hal/maxim/
H A DhalCHIP.c441 IRQ_REG(REG_IRQEXP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
458 IRQ_REG(REG_IRQEXP_MASK_L) &= ~(0x1 << (u8VectorIndex-E_IRQEXPL_START) ); in CHIP_EnableIRQ()
500 IRQ_REG(REG_IRQEXP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
517 IRQ_REG(REG_IRQEXP_MASK_L) |= (0x1 << (u8VectorIndex-E_IRQEXPL_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h149 #define REG_IRQEXP_MASK_L 0x0036 macro
174 #define REG_IRQEXP_MASK_L 0x0036 macro
/utopia/UTPA2-700.0.x/mxlib/hal/marcus/
H A DhalCHIP.c441 IRQ_REG(REG_IRQEXP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
458 IRQ_REG(REG_IRQEXP_MASK_L) &= ~(0x1 << (u8VectorIndex-E_IRQEXPL_START) ); in CHIP_EnableIRQ()
500 IRQ_REG(REG_IRQEXP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
517 IRQ_REG(REG_IRQEXP_MASK_L) |= (0x1 << (u8VectorIndex-E_IRQEXPL_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h149 #define REG_IRQEXP_MASK_L 0x0036 macro
174 #define REG_IRQEXP_MASK_L 0x0036 macro
/utopia/UTPA2-700.0.x/mxlib/hal/mainz/
H A DhalCHIP.c424 IRQ_REG(REG_IRQEXP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
441 IRQ_REG(REG_IRQEXP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_IRQEXPL_START)); in CHIP_EnableIRQ()
482 IRQ_REG(REG_IRQEXP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
499 IRQ_REG(REG_IRQEXP_MASK_L) |= (0x01 << (u8VectorIndex - E_IRQEXPL_START)); in CHIP_DisableIRQ()
/utopia/UTPA2-700.0.x/mxlib/hal/maserati/
H A DhalCHIP.c441 IRQ_REG(REG_IRQEXP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
458 IRQ_REG(REG_IRQEXP_MASK_L) &= ~(0x1 << (u8VectorIndex-E_IRQEXPL_START) ); in CHIP_EnableIRQ()
500 IRQ_REG(REG_IRQEXP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
517 IRQ_REG(REG_IRQEXP_MASK_L) |= (0x1 << (u8VectorIndex-E_IRQEXPL_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h149 #define REG_IRQEXP_MASK_L 0x0036 macro
174 #define REG_IRQEXP_MASK_L 0x0036 macro
/utopia/UTPA2-700.0.x/mxlib/hal/manhattan/
H A DhalCHIP.c441 IRQ_REG(REG_IRQEXP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
458 IRQ_REG(REG_IRQEXP_MASK_L) &= ~(0x1 << (u8VectorIndex-E_IRQEXPL_START) ); in CHIP_EnableIRQ()
500 IRQ_REG(REG_IRQEXP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
517 IRQ_REG(REG_IRQEXP_MASK_L) |= (0x1 << (u8VectorIndex-E_IRQEXPL_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h149 #define REG_IRQEXP_MASK_L 0x0036 macro
174 #define REG_IRQEXP_MASK_L 0x0036 macro
/utopia/UTPA2-700.0.x/mxlib/hal/mustang/
H A DhalCHIP.c424 IRQ_REG(REG_IRQEXP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
441 IRQ_REG(REG_IRQEXP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_IRQEXPL_START)); in CHIP_EnableIRQ()
482 IRQ_REG(REG_IRQEXP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
499 IRQ_REG(REG_IRQEXP_MASK_L) |= (0x01 << (u8VectorIndex - E_IRQEXPL_START)); in CHIP_DisableIRQ()
/utopia/UTPA2-700.0.x/mxlib/hal/messi/
H A DhalCHIP.c424 IRQ_REG(REG_IRQEXP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
441 IRQ_REG(REG_IRQEXP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_IRQEXPL_START)); in CHIP_EnableIRQ()
482 IRQ_REG(REG_IRQEXP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
499 IRQ_REG(REG_IRQEXP_MASK_L) |= (0x01 << (u8VectorIndex - E_IRQEXPL_START)); in CHIP_DisableIRQ()
/utopia/UTPA2-700.0.x/mxlib/hal/M7621/
H A DhalCHIP.c441 IRQ_REG(REG_IRQEXP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
458 IRQ_REG(REG_IRQEXP_MASK_L) &= ~(0x1 << (u8VectorIndex-E_IRQEXPL_START) ); in CHIP_EnableIRQ()
500 IRQ_REG(REG_IRQEXP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
517 IRQ_REG(REG_IRQEXP_MASK_L) |= (0x1 << (u8VectorIndex-E_IRQEXPL_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h149 #define REG_IRQEXP_MASK_L 0x0036 macro
176 #define REG_IRQEXP_MASK_L 0x0036 macro

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