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Searched refs:REG_IRQEXP_MASK_H (Results 1 – 25 of 28) sorted by relevance

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/utopia/UTPA2-700.0.x/mxlib/hal/k7u/
H A DhalCHIP.c510 IRQ_REG(REG_IRQEXP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
535 IRQ_REG(REG_IRQEXP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQEXPH_START)); in CHIP_EnableIRQ()
589 IRQ_REG(REG_IRQEXP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
614 IRQ_REG(REG_IRQEXP_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQEXPH_START)); in CHIP_DisableIRQ()
1646 IRQ_REG(REG_IRQEXP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
1671 IRQ_REG(REG_IRQEXP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQEXPH_START)); in CHIP_EnableIRQ()
1725 IRQ_REG(REG_IRQEXP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
1750 IRQ_REG(REG_IRQEXP_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQEXPH_START)); in CHIP_DisableIRQ()
H A DregCHIP.h131 #define REG_IRQEXP_MASK_H 0x0037 macro
175 #define REG_IRQEXP_MASK_H (REG_INT_BASE_ADDR + 0x0017) macro
/utopia/UTPA2-700.0.x/mxlib/hal/k6lite/
H A DhalCHIP.c510 IRQ_REG(REG_IRQEXP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
535 IRQ_REG(REG_IRQEXP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQEXPH_START)); in CHIP_EnableIRQ()
589 IRQ_REG(REG_IRQEXP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
614 IRQ_REG(REG_IRQEXP_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQEXPH_START)); in CHIP_DisableIRQ()
1646 IRQ_REG(REG_IRQEXP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
1671 IRQ_REG(REG_IRQEXP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQEXPH_START)); in CHIP_EnableIRQ()
1725 IRQ_REG(REG_IRQEXP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
1750 IRQ_REG(REG_IRQEXP_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQEXPH_START)); in CHIP_DisableIRQ()
H A DregCHIP.h131 #define REG_IRQEXP_MASK_H 0x0037 macro
175 #define REG_IRQEXP_MASK_H (REG_INT_BASE_ADDR + 0x0017) macro
/utopia/UTPA2-700.0.x/mxlib/hal/curry/
H A DhalCHIP.c510 IRQ_REG(REG_IRQEXP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
535 IRQ_REG(REG_IRQEXP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQEXPH_START)); in CHIP_EnableIRQ()
589 IRQ_REG(REG_IRQEXP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
614 IRQ_REG(REG_IRQEXP_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQEXPH_START)); in CHIP_DisableIRQ()
1633 IRQ_REG(REG_IRQEXP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
1658 IRQ_REG(REG_IRQEXP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQEXPH_START)); in CHIP_EnableIRQ()
1712 IRQ_REG(REG_IRQEXP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
1737 IRQ_REG(REG_IRQEXP_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQEXPH_START)); in CHIP_DisableIRQ()
H A DregCHIP.h131 #define REG_IRQEXP_MASK_H 0x0037 macro
175 #define REG_IRQEXP_MASK_H (REG_INT_BASE_ADDR + 0x0017) macro
/utopia/UTPA2-700.0.x/mxlib/hal/kano/
H A DhalCHIP.c510 IRQ_REG(REG_IRQEXP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
535 IRQ_REG(REG_IRQEXP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQEXPH_START)); in CHIP_EnableIRQ()
589 IRQ_REG(REG_IRQEXP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
614 IRQ_REG(REG_IRQEXP_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQEXPH_START)); in CHIP_DisableIRQ()
1646 IRQ_REG(REG_IRQEXP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
1671 IRQ_REG(REG_IRQEXP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQEXPH_START)); in CHIP_EnableIRQ()
1725 IRQ_REG(REG_IRQEXP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
1750 IRQ_REG(REG_IRQEXP_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQEXPH_START)); in CHIP_DisableIRQ()
H A DregCHIP.h131 #define REG_IRQEXP_MASK_H 0x0037 macro
175 #define REG_IRQEXP_MASK_H (REG_INT_BASE_ADDR + 0x0017) macro
/utopia/UTPA2-700.0.x/mxlib/hal/k6/
H A DhalCHIP.c510 IRQ_REG(REG_IRQEXP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
535 IRQ_REG(REG_IRQEXP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQEXPH_START)); in CHIP_EnableIRQ()
589 IRQ_REG(REG_IRQEXP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
614 IRQ_REG(REG_IRQEXP_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQEXPH_START)); in CHIP_DisableIRQ()
1646 IRQ_REG(REG_IRQEXP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
1671 IRQ_REG(REG_IRQEXP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQEXPH_START)); in CHIP_EnableIRQ()
1725 IRQ_REG(REG_IRQEXP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
1750 IRQ_REG(REG_IRQEXP_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQEXPH_START)); in CHIP_DisableIRQ()
H A DregCHIP.h131 #define REG_IRQEXP_MASK_H 0x0037 macro
175 #define REG_IRQEXP_MASK_H (REG_INT_BASE_ADDR + 0x0017) macro
/utopia/UTPA2-700.0.x/mxlib/hal/M7821/
H A DhalCHIP.c442 IRQ_REG(REG_IRQEXP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
462 IRQ_REG(REG_IRQEXP_MASK_H) &= ~(0x1 << (u8VectorIndex-E_IRQEXPH_START) ); in CHIP_EnableIRQ()
501 IRQ_REG(REG_IRQEXP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
521 IRQ_REG(REG_IRQEXP_MASK_H) |= (0x1 << (u8VectorIndex-E_IRQEXPH_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h150 #define REG_IRQEXP_MASK_H 0x0037 macro
177 #define REG_IRQEXP_MASK_H 0x0037 macro
/utopia/UTPA2-700.0.x/mxlib/hal/maxim/
H A DhalCHIP.c442 IRQ_REG(REG_IRQEXP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
462 IRQ_REG(REG_IRQEXP_MASK_H) &= ~(0x1 << (u8VectorIndex-E_IRQEXPH_START) ); in CHIP_EnableIRQ()
501 IRQ_REG(REG_IRQEXP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
521 IRQ_REG(REG_IRQEXP_MASK_H) |= (0x1 << (u8VectorIndex-E_IRQEXPH_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h150 #define REG_IRQEXP_MASK_H 0x0037 macro
175 #define REG_IRQEXP_MASK_H 0x0037 macro
/utopia/UTPA2-700.0.x/mxlib/hal/marcus/
H A DhalCHIP.c442 IRQ_REG(REG_IRQEXP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
462 IRQ_REG(REG_IRQEXP_MASK_H) &= ~(0x1 << (u8VectorIndex-E_IRQEXPH_START) ); in CHIP_EnableIRQ()
501 IRQ_REG(REG_IRQEXP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
521 IRQ_REG(REG_IRQEXP_MASK_H) |= (0x1 << (u8VectorIndex-E_IRQEXPH_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h150 #define REG_IRQEXP_MASK_H 0x0037 macro
175 #define REG_IRQEXP_MASK_H 0x0037 macro
/utopia/UTPA2-700.0.x/mxlib/hal/mainz/
H A DhalCHIP.c425 IRQ_REG(REG_IRQEXP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
445 IRQ_REG(REG_IRQEXP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQEXPH_START)); in CHIP_EnableIRQ()
483 IRQ_REG(REG_IRQEXP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
503 IRQ_REG(REG_IRQEXP_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQEXPH_START)); in CHIP_DisableIRQ()
/utopia/UTPA2-700.0.x/mxlib/hal/maserati/
H A DhalCHIP.c442 IRQ_REG(REG_IRQEXP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
462 IRQ_REG(REG_IRQEXP_MASK_H) &= ~(0x1 << (u8VectorIndex-E_IRQEXPH_START) ); in CHIP_EnableIRQ()
501 IRQ_REG(REG_IRQEXP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
521 IRQ_REG(REG_IRQEXP_MASK_H) |= (0x1 << (u8VectorIndex-E_IRQEXPH_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h150 #define REG_IRQEXP_MASK_H 0x0037 macro
175 #define REG_IRQEXP_MASK_H 0x0037 macro
/utopia/UTPA2-700.0.x/mxlib/hal/manhattan/
H A DhalCHIP.c442 IRQ_REG(REG_IRQEXP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
462 IRQ_REG(REG_IRQEXP_MASK_H) &= ~(0x1 << (u8VectorIndex-E_IRQEXPH_START) ); in CHIP_EnableIRQ()
501 IRQ_REG(REG_IRQEXP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
521 IRQ_REG(REG_IRQEXP_MASK_H) |= (0x1 << (u8VectorIndex-E_IRQEXPH_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h150 #define REG_IRQEXP_MASK_H 0x0037 macro
175 #define REG_IRQEXP_MASK_H 0x0037 macro
/utopia/UTPA2-700.0.x/mxlib/hal/mustang/
H A DhalCHIP.c425 IRQ_REG(REG_IRQEXP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
445 IRQ_REG(REG_IRQEXP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQEXPH_START)); in CHIP_EnableIRQ()
483 IRQ_REG(REG_IRQEXP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
503 IRQ_REG(REG_IRQEXP_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQEXPH_START)); in CHIP_DisableIRQ()
/utopia/UTPA2-700.0.x/mxlib/hal/messi/
H A DhalCHIP.c425 IRQ_REG(REG_IRQEXP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
445 IRQ_REG(REG_IRQEXP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQEXPH_START)); in CHIP_EnableIRQ()
483 IRQ_REG(REG_IRQEXP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
503 IRQ_REG(REG_IRQEXP_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQEXPH_START)); in CHIP_DisableIRQ()
/utopia/UTPA2-700.0.x/mxlib/hal/M7621/
H A DhalCHIP.c442 IRQ_REG(REG_IRQEXP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
462 IRQ_REG(REG_IRQEXP_MASK_H) &= ~(0x1 << (u8VectorIndex-E_IRQEXPH_START) ); in CHIP_EnableIRQ()
501 IRQ_REG(REG_IRQEXP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
521 IRQ_REG(REG_IRQEXP_MASK_H) |= (0x1 << (u8VectorIndex-E_IRQEXPH_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h150 #define REG_IRQEXP_MASK_H 0x0037 macro
177 #define REG_IRQEXP_MASK_H 0x0037 macro

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