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Searched refs:REG_HDMI3_DUAL_0_BASE (Results 1 – 25 of 27) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h6225 #define REG_HDMI3_DUAL_0_00_L (REG_HDMI3_DUAL_0_BASE + 0x00)
6226 #define REG_HDMI3_DUAL_0_00_H (REG_HDMI3_DUAL_0_BASE + 0x01)
6227 #define REG_HDMI3_DUAL_0_01_L (REG_HDMI3_DUAL_0_BASE + 0x02)
6228 #define REG_HDMI3_DUAL_0_01_H (REG_HDMI3_DUAL_0_BASE + 0x03)
6229 #define REG_HDMI3_DUAL_0_02_L (REG_HDMI3_DUAL_0_BASE + 0x04)
6230 #define REG_HDMI3_DUAL_0_02_H (REG_HDMI3_DUAL_0_BASE + 0x05)
6231 #define REG_HDMI3_DUAL_0_03_L (REG_HDMI3_DUAL_0_BASE + 0x06)
6232 #define REG_HDMI3_DUAL_0_03_H (REG_HDMI3_DUAL_0_BASE + 0x07)
6233 #define REG_HDMI3_DUAL_0_04_L (REG_HDMI3_DUAL_0_BASE + 0x08)
6234 #define REG_HDMI3_DUAL_0_04_H (REG_HDMI3_DUAL_0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h603 #define REG_HDMI3_DUAL_0_BASE 0x173400UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h6227 #define REG_HDMI3_DUAL_0_00_L (REG_HDMI3_DUAL_0_BASE + 0x00)
6228 #define REG_HDMI3_DUAL_0_00_H (REG_HDMI3_DUAL_0_BASE + 0x01)
6229 #define REG_HDMI3_DUAL_0_01_L (REG_HDMI3_DUAL_0_BASE + 0x02)
6230 #define REG_HDMI3_DUAL_0_01_H (REG_HDMI3_DUAL_0_BASE + 0x03)
6231 #define REG_HDMI3_DUAL_0_02_L (REG_HDMI3_DUAL_0_BASE + 0x04)
6232 #define REG_HDMI3_DUAL_0_02_H (REG_HDMI3_DUAL_0_BASE + 0x05)
6233 #define REG_HDMI3_DUAL_0_03_L (REG_HDMI3_DUAL_0_BASE + 0x06)
6234 #define REG_HDMI3_DUAL_0_03_H (REG_HDMI3_DUAL_0_BASE + 0x07)
6235 #define REG_HDMI3_DUAL_0_04_L (REG_HDMI3_DUAL_0_BASE + 0x08)
6236 #define REG_HDMI3_DUAL_0_04_H (REG_HDMI3_DUAL_0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h585 #define REG_HDMI3_DUAL_0_BASE 0x173400UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h6217 #define REG_HDMI3_DUAL_0_00_L (REG_HDMI3_DUAL_0_BASE + 0x00)
6218 #define REG_HDMI3_DUAL_0_00_H (REG_HDMI3_DUAL_0_BASE + 0x01)
6219 #define REG_HDMI3_DUAL_0_01_L (REG_HDMI3_DUAL_0_BASE + 0x02)
6220 #define REG_HDMI3_DUAL_0_01_H (REG_HDMI3_DUAL_0_BASE + 0x03)
6221 #define REG_HDMI3_DUAL_0_02_L (REG_HDMI3_DUAL_0_BASE + 0x04)
6222 #define REG_HDMI3_DUAL_0_02_H (REG_HDMI3_DUAL_0_BASE + 0x05)
6223 #define REG_HDMI3_DUAL_0_03_L (REG_HDMI3_DUAL_0_BASE + 0x06)
6224 #define REG_HDMI3_DUAL_0_03_H (REG_HDMI3_DUAL_0_BASE + 0x07)
6225 #define REG_HDMI3_DUAL_0_04_L (REG_HDMI3_DUAL_0_BASE + 0x08)
6226 #define REG_HDMI3_DUAL_0_04_H (REG_HDMI3_DUAL_0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h563 #define REG_HDMI3_DUAL_0_BASE 0x173400UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h6227 #define REG_HDMI3_DUAL_0_00_L (REG_HDMI3_DUAL_0_BASE + 0x00)
6228 #define REG_HDMI3_DUAL_0_00_H (REG_HDMI3_DUAL_0_BASE + 0x01)
6229 #define REG_HDMI3_DUAL_0_01_L (REG_HDMI3_DUAL_0_BASE + 0x02)
6230 #define REG_HDMI3_DUAL_0_01_H (REG_HDMI3_DUAL_0_BASE + 0x03)
6231 #define REG_HDMI3_DUAL_0_02_L (REG_HDMI3_DUAL_0_BASE + 0x04)
6232 #define REG_HDMI3_DUAL_0_02_H (REG_HDMI3_DUAL_0_BASE + 0x05)
6233 #define REG_HDMI3_DUAL_0_03_L (REG_HDMI3_DUAL_0_BASE + 0x06)
6234 #define REG_HDMI3_DUAL_0_03_H (REG_HDMI3_DUAL_0_BASE + 0x07)
6235 #define REG_HDMI3_DUAL_0_04_L (REG_HDMI3_DUAL_0_BASE + 0x08)
6236 #define REG_HDMI3_DUAL_0_04_H (REG_HDMI3_DUAL_0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h587 #define REG_HDMI3_DUAL_0_BASE 0x173400UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h6217 #define REG_HDMI3_DUAL_0_00_L (REG_HDMI3_DUAL_0_BASE + 0x00)
6218 #define REG_HDMI3_DUAL_0_00_H (REG_HDMI3_DUAL_0_BASE + 0x01)
6219 #define REG_HDMI3_DUAL_0_01_L (REG_HDMI3_DUAL_0_BASE + 0x02)
6220 #define REG_HDMI3_DUAL_0_01_H (REG_HDMI3_DUAL_0_BASE + 0x03)
6221 #define REG_HDMI3_DUAL_0_02_L (REG_HDMI3_DUAL_0_BASE + 0x04)
6222 #define REG_HDMI3_DUAL_0_02_H (REG_HDMI3_DUAL_0_BASE + 0x05)
6223 #define REG_HDMI3_DUAL_0_03_L (REG_HDMI3_DUAL_0_BASE + 0x06)
6224 #define REG_HDMI3_DUAL_0_03_H (REG_HDMI3_DUAL_0_BASE + 0x07)
6225 #define REG_HDMI3_DUAL_0_04_L (REG_HDMI3_DUAL_0_BASE + 0x08)
6226 #define REG_HDMI3_DUAL_0_04_H (REG_HDMI3_DUAL_0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h590 #define REG_HDMI3_DUAL_0_BASE 0x173400UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h6227 #define REG_HDMI3_DUAL_0_00_L (REG_HDMI3_DUAL_0_BASE + 0x00)
6228 #define REG_HDMI3_DUAL_0_00_H (REG_HDMI3_DUAL_0_BASE + 0x01)
6229 #define REG_HDMI3_DUAL_0_01_L (REG_HDMI3_DUAL_0_BASE + 0x02)
6230 #define REG_HDMI3_DUAL_0_01_H (REG_HDMI3_DUAL_0_BASE + 0x03)
6231 #define REG_HDMI3_DUAL_0_02_L (REG_HDMI3_DUAL_0_BASE + 0x04)
6232 #define REG_HDMI3_DUAL_0_02_H (REG_HDMI3_DUAL_0_BASE + 0x05)
6233 #define REG_HDMI3_DUAL_0_03_L (REG_HDMI3_DUAL_0_BASE + 0x06)
6234 #define REG_HDMI3_DUAL_0_03_H (REG_HDMI3_DUAL_0_BASE + 0x07)
6235 #define REG_HDMI3_DUAL_0_04_L (REG_HDMI3_DUAL_0_BASE + 0x08)
6236 #define REG_HDMI3_DUAL_0_04_H (REG_HDMI3_DUAL_0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h579 #define REG_HDMI3_DUAL_0_BASE 0x173400UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h6227 #define REG_HDMI3_DUAL_0_00_L (REG_HDMI3_DUAL_0_BASE + 0x00)
6228 #define REG_HDMI3_DUAL_0_00_H (REG_HDMI3_DUAL_0_BASE + 0x01)
6229 #define REG_HDMI3_DUAL_0_01_L (REG_HDMI3_DUAL_0_BASE + 0x02)
6230 #define REG_HDMI3_DUAL_0_01_H (REG_HDMI3_DUAL_0_BASE + 0x03)
6231 #define REG_HDMI3_DUAL_0_02_L (REG_HDMI3_DUAL_0_BASE + 0x04)
6232 #define REG_HDMI3_DUAL_0_02_H (REG_HDMI3_DUAL_0_BASE + 0x05)
6233 #define REG_HDMI3_DUAL_0_03_L (REG_HDMI3_DUAL_0_BASE + 0x06)
6234 #define REG_HDMI3_DUAL_0_03_H (REG_HDMI3_DUAL_0_BASE + 0x07)
6235 #define REG_HDMI3_DUAL_0_04_L (REG_HDMI3_DUAL_0_BASE + 0x08)
6236 #define REG_HDMI3_DUAL_0_04_H (REG_HDMI3_DUAL_0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h585 #define REG_HDMI3_DUAL_0_BASE 0x173400UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h6217 #define REG_HDMI3_DUAL_0_00_L (REG_HDMI3_DUAL_0_BASE + 0x00)
6218 #define REG_HDMI3_DUAL_0_00_H (REG_HDMI3_DUAL_0_BASE + 0x01)
6219 #define REG_HDMI3_DUAL_0_01_L (REG_HDMI3_DUAL_0_BASE + 0x02)
6220 #define REG_HDMI3_DUAL_0_01_H (REG_HDMI3_DUAL_0_BASE + 0x03)
6221 #define REG_HDMI3_DUAL_0_02_L (REG_HDMI3_DUAL_0_BASE + 0x04)
6222 #define REG_HDMI3_DUAL_0_02_H (REG_HDMI3_DUAL_0_BASE + 0x05)
6223 #define REG_HDMI3_DUAL_0_03_L (REG_HDMI3_DUAL_0_BASE + 0x06)
6224 #define REG_HDMI3_DUAL_0_03_H (REG_HDMI3_DUAL_0_BASE + 0x07)
6225 #define REG_HDMI3_DUAL_0_04_L (REG_HDMI3_DUAL_0_BASE + 0x08)
6226 #define REG_HDMI3_DUAL_0_04_H (REG_HDMI3_DUAL_0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h561 #define REG_HDMI3_DUAL_0_BASE 0x173400UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h6218 #define REG_HDMI3_DUAL_0_00_L (REG_HDMI3_DUAL_0_BASE + 0x00)
6219 #define REG_HDMI3_DUAL_0_00_H (REG_HDMI3_DUAL_0_BASE + 0x01)
6220 #define REG_HDMI3_DUAL_0_01_L (REG_HDMI3_DUAL_0_BASE + 0x02)
6221 #define REG_HDMI3_DUAL_0_01_H (REG_HDMI3_DUAL_0_BASE + 0x03)
6222 #define REG_HDMI3_DUAL_0_02_L (REG_HDMI3_DUAL_0_BASE + 0x04)
6223 #define REG_HDMI3_DUAL_0_02_H (REG_HDMI3_DUAL_0_BASE + 0x05)
6224 #define REG_HDMI3_DUAL_0_03_L (REG_HDMI3_DUAL_0_BASE + 0x06)
6225 #define REG_HDMI3_DUAL_0_03_H (REG_HDMI3_DUAL_0_BASE + 0x07)
6226 #define REG_HDMI3_DUAL_0_04_L (REG_HDMI3_DUAL_0_BASE + 0x08)
6227 #define REG_HDMI3_DUAL_0_04_H (REG_HDMI3_DUAL_0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h544 #define REG_HDMI3_DUAL_0_BASE 0x173400UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h6217 #define REG_HDMI3_DUAL_0_00_L (REG_HDMI3_DUAL_0_BASE + 0x00)
6218 #define REG_HDMI3_DUAL_0_00_H (REG_HDMI3_DUAL_0_BASE + 0x01)
6219 #define REG_HDMI3_DUAL_0_01_L (REG_HDMI3_DUAL_0_BASE + 0x02)
6220 #define REG_HDMI3_DUAL_0_01_H (REG_HDMI3_DUAL_0_BASE + 0x03)
6221 #define REG_HDMI3_DUAL_0_02_L (REG_HDMI3_DUAL_0_BASE + 0x04)
6222 #define REG_HDMI3_DUAL_0_02_H (REG_HDMI3_DUAL_0_BASE + 0x05)
6223 #define REG_HDMI3_DUAL_0_03_L (REG_HDMI3_DUAL_0_BASE + 0x06)
6224 #define REG_HDMI3_DUAL_0_03_H (REG_HDMI3_DUAL_0_BASE + 0x07)
6225 #define REG_HDMI3_DUAL_0_04_L (REG_HDMI3_DUAL_0_BASE + 0x08)
6226 #define REG_HDMI3_DUAL_0_04_H (REG_HDMI3_DUAL_0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h637 #define REG_HDMI3_DUAL_0_BASE 0x173400UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h6225 #define REG_HDMI3_DUAL_0_00_L (REG_HDMI3_DUAL_0_BASE + 0x00)
6226 #define REG_HDMI3_DUAL_0_00_H (REG_HDMI3_DUAL_0_BASE + 0x01)
6227 #define REG_HDMI3_DUAL_0_01_L (REG_HDMI3_DUAL_0_BASE + 0x02)
6228 #define REG_HDMI3_DUAL_0_01_H (REG_HDMI3_DUAL_0_BASE + 0x03)
6229 #define REG_HDMI3_DUAL_0_02_L (REG_HDMI3_DUAL_0_BASE + 0x04)
6230 #define REG_HDMI3_DUAL_0_02_H (REG_HDMI3_DUAL_0_BASE + 0x05)
6231 #define REG_HDMI3_DUAL_0_03_L (REG_HDMI3_DUAL_0_BASE + 0x06)
6232 #define REG_HDMI3_DUAL_0_03_H (REG_HDMI3_DUAL_0_BASE + 0x07)
6233 #define REG_HDMI3_DUAL_0_04_L (REG_HDMI3_DUAL_0_BASE + 0x08)
6234 #define REG_HDMI3_DUAL_0_04_H (REG_HDMI3_DUAL_0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h649 #define REG_HDMI3_DUAL_0_BASE 0x173400UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h6225 #define REG_HDMI3_DUAL_0_00_L (REG_HDMI3_DUAL_0_BASE + 0x00)
6226 #define REG_HDMI3_DUAL_0_00_H (REG_HDMI3_DUAL_0_BASE + 0x01)
6227 #define REG_HDMI3_DUAL_0_01_L (REG_HDMI3_DUAL_0_BASE + 0x02)
6228 #define REG_HDMI3_DUAL_0_01_H (REG_HDMI3_DUAL_0_BASE + 0x03)
6229 #define REG_HDMI3_DUAL_0_02_L (REG_HDMI3_DUAL_0_BASE + 0x04)
6230 #define REG_HDMI3_DUAL_0_02_H (REG_HDMI3_DUAL_0_BASE + 0x05)
6231 #define REG_HDMI3_DUAL_0_03_L (REG_HDMI3_DUAL_0_BASE + 0x06)
6232 #define REG_HDMI3_DUAL_0_03_H (REG_HDMI3_DUAL_0_BASE + 0x07)
6233 #define REG_HDMI3_DUAL_0_04_L (REG_HDMI3_DUAL_0_BASE + 0x08)
6234 #define REG_HDMI3_DUAL_0_04_H (REG_HDMI3_DUAL_0_BASE + 0x09)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_hdmi.h6225 #define REG_HDMI3_DUAL_0_00_L (REG_HDMI3_DUAL_0_BASE + 0x00)
6226 #define REG_HDMI3_DUAL_0_00_H (REG_HDMI3_DUAL_0_BASE + 0x01)
6227 #define REG_HDMI3_DUAL_0_01_L (REG_HDMI3_DUAL_0_BASE + 0x02)
6228 #define REG_HDMI3_DUAL_0_01_H (REG_HDMI3_DUAL_0_BASE + 0x03)
6229 #define REG_HDMI3_DUAL_0_02_L (REG_HDMI3_DUAL_0_BASE + 0x04)
6230 #define REG_HDMI3_DUAL_0_02_H (REG_HDMI3_DUAL_0_BASE + 0x05)
6231 #define REG_HDMI3_DUAL_0_03_L (REG_HDMI3_DUAL_0_BASE + 0x06)
6232 #define REG_HDMI3_DUAL_0_03_H (REG_HDMI3_DUAL_0_BASE + 0x07)
6233 #define REG_HDMI3_DUAL_0_04_L (REG_HDMI3_DUAL_0_BASE + 0x08)
6234 #define REG_HDMI3_DUAL_0_04_H (REG_HDMI3_DUAL_0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h654 #define REG_HDMI3_DUAL_0_BASE 0x173400UL macro

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