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Searched refs:REG_HDCP_DUAL_P3_BASE (Results 1 – 25 of 27) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h5495 #define REG_HDCP_DUAL_P3_00_L (REG_HDCP_DUAL_P3_BASE + 0x00)
5496 #define REG_HDCP_DUAL_P3_00_H (REG_HDCP_DUAL_P3_BASE + 0x01)
5497 #define REG_HDCP_DUAL_P3_01_L (REG_HDCP_DUAL_P3_BASE + 0x02)
5498 #define REG_HDCP_DUAL_P3_01_H (REG_HDCP_DUAL_P3_BASE + 0x03)
5499 #define REG_HDCP_DUAL_P3_02_L (REG_HDCP_DUAL_P3_BASE + 0x04)
5500 #define REG_HDCP_DUAL_P3_02_H (REG_HDCP_DUAL_P3_BASE + 0x05)
5501 #define REG_HDCP_DUAL_P3_03_L (REG_HDCP_DUAL_P3_BASE + 0x06)
5502 #define REG_HDCP_DUAL_P3_03_H (REG_HDCP_DUAL_P3_BASE + 0x07)
5503 #define REG_HDCP_DUAL_P3_04_L (REG_HDCP_DUAL_P3_BASE + 0x08)
5504 #define REG_HDCP_DUAL_P3_04_H (REG_HDCP_DUAL_P3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h599 #define REG_HDCP_DUAL_P3_BASE 0x171B00UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h5497 #define REG_HDCP_DUAL_P3_00_L (REG_HDCP_DUAL_P3_BASE + 0x00)
5498 #define REG_HDCP_DUAL_P3_00_H (REG_HDCP_DUAL_P3_BASE + 0x01)
5499 #define REG_HDCP_DUAL_P3_01_L (REG_HDCP_DUAL_P3_BASE + 0x02)
5500 #define REG_HDCP_DUAL_P3_01_H (REG_HDCP_DUAL_P3_BASE + 0x03)
5501 #define REG_HDCP_DUAL_P3_02_L (REG_HDCP_DUAL_P3_BASE + 0x04)
5502 #define REG_HDCP_DUAL_P3_02_H (REG_HDCP_DUAL_P3_BASE + 0x05)
5503 #define REG_HDCP_DUAL_P3_03_L (REG_HDCP_DUAL_P3_BASE + 0x06)
5504 #define REG_HDCP_DUAL_P3_03_H (REG_HDCP_DUAL_P3_BASE + 0x07)
5505 #define REG_HDCP_DUAL_P3_04_L (REG_HDCP_DUAL_P3_BASE + 0x08)
5506 #define REG_HDCP_DUAL_P3_04_H (REG_HDCP_DUAL_P3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h581 #define REG_HDCP_DUAL_P3_BASE REG_HDCP_DUAL_P0_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h5497 #define REG_HDCP_DUAL_P3_00_L (REG_HDCP_DUAL_P3_BASE + 0x00)
5498 #define REG_HDCP_DUAL_P3_00_H (REG_HDCP_DUAL_P3_BASE + 0x01)
5499 #define REG_HDCP_DUAL_P3_01_L (REG_HDCP_DUAL_P3_BASE + 0x02)
5500 #define REG_HDCP_DUAL_P3_01_H (REG_HDCP_DUAL_P3_BASE + 0x03)
5501 #define REG_HDCP_DUAL_P3_02_L (REG_HDCP_DUAL_P3_BASE + 0x04)
5502 #define REG_HDCP_DUAL_P3_02_H (REG_HDCP_DUAL_P3_BASE + 0x05)
5503 #define REG_HDCP_DUAL_P3_03_L (REG_HDCP_DUAL_P3_BASE + 0x06)
5504 #define REG_HDCP_DUAL_P3_03_H (REG_HDCP_DUAL_P3_BASE + 0x07)
5505 #define REG_HDCP_DUAL_P3_04_L (REG_HDCP_DUAL_P3_BASE + 0x08)
5506 #define REG_HDCP_DUAL_P3_04_H (REG_HDCP_DUAL_P3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h583 #define REG_HDCP_DUAL_P3_BASE REG_HDCP_DUAL_P0_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h5497 #define REG_HDCP_DUAL_P3_00_L (REG_HDCP_DUAL_P3_BASE + 0x00)
5498 #define REG_HDCP_DUAL_P3_00_H (REG_HDCP_DUAL_P3_BASE + 0x01)
5499 #define REG_HDCP_DUAL_P3_01_L (REG_HDCP_DUAL_P3_BASE + 0x02)
5500 #define REG_HDCP_DUAL_P3_01_H (REG_HDCP_DUAL_P3_BASE + 0x03)
5501 #define REG_HDCP_DUAL_P3_02_L (REG_HDCP_DUAL_P3_BASE + 0x04)
5502 #define REG_HDCP_DUAL_P3_02_H (REG_HDCP_DUAL_P3_BASE + 0x05)
5503 #define REG_HDCP_DUAL_P3_03_L (REG_HDCP_DUAL_P3_BASE + 0x06)
5504 #define REG_HDCP_DUAL_P3_03_H (REG_HDCP_DUAL_P3_BASE + 0x07)
5505 #define REG_HDCP_DUAL_P3_04_L (REG_HDCP_DUAL_P3_BASE + 0x08)
5506 #define REG_HDCP_DUAL_P3_04_H (REG_HDCP_DUAL_P3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h575 #define REG_HDCP_DUAL_P3_BASE REG_HDCP_DUAL_P0_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h5497 #define REG_HDCP_DUAL_P3_00_L (REG_HDCP_DUAL_P3_BASE + 0x00)
5498 #define REG_HDCP_DUAL_P3_00_H (REG_HDCP_DUAL_P3_BASE + 0x01)
5499 #define REG_HDCP_DUAL_P3_01_L (REG_HDCP_DUAL_P3_BASE + 0x02)
5500 #define REG_HDCP_DUAL_P3_01_H (REG_HDCP_DUAL_P3_BASE + 0x03)
5501 #define REG_HDCP_DUAL_P3_02_L (REG_HDCP_DUAL_P3_BASE + 0x04)
5502 #define REG_HDCP_DUAL_P3_02_H (REG_HDCP_DUAL_P3_BASE + 0x05)
5503 #define REG_HDCP_DUAL_P3_03_L (REG_HDCP_DUAL_P3_BASE + 0x06)
5504 #define REG_HDCP_DUAL_P3_03_H (REG_HDCP_DUAL_P3_BASE + 0x07)
5505 #define REG_HDCP_DUAL_P3_04_L (REG_HDCP_DUAL_P3_BASE + 0x08)
5506 #define REG_HDCP_DUAL_P3_04_H (REG_HDCP_DUAL_P3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h581 #define REG_HDCP_DUAL_P3_BASE REG_HDCP_DUAL_P0_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h5489 #define REG_HDCP_DUAL_P3_00_L (REG_HDCP_DUAL_P3_BASE + 0x00)
5490 #define REG_HDCP_DUAL_P3_00_H (REG_HDCP_DUAL_P3_BASE + 0x01)
5491 #define REG_HDCP_DUAL_P3_01_L (REG_HDCP_DUAL_P3_BASE + 0x02)
5492 #define REG_HDCP_DUAL_P3_01_H (REG_HDCP_DUAL_P3_BASE + 0x03)
5493 #define REG_HDCP_DUAL_P3_02_L (REG_HDCP_DUAL_P3_BASE + 0x04)
5494 #define REG_HDCP_DUAL_P3_02_H (REG_HDCP_DUAL_P3_BASE + 0x05)
5495 #define REG_HDCP_DUAL_P3_03_L (REG_HDCP_DUAL_P3_BASE + 0x06)
5496 #define REG_HDCP_DUAL_P3_03_H (REG_HDCP_DUAL_P3_BASE + 0x07)
5497 #define REG_HDCP_DUAL_P3_04_L (REG_HDCP_DUAL_P3_BASE + 0x08)
5498 #define REG_HDCP_DUAL_P3_04_H (REG_HDCP_DUAL_P3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h559 #define REG_HDCP_DUAL_P3_BASE 0x171B00UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h5489 #define REG_HDCP_DUAL_P3_00_L (REG_HDCP_DUAL_P3_BASE + 0x00)
5490 #define REG_HDCP_DUAL_P3_00_H (REG_HDCP_DUAL_P3_BASE + 0x01)
5491 #define REG_HDCP_DUAL_P3_01_L (REG_HDCP_DUAL_P3_BASE + 0x02)
5492 #define REG_HDCP_DUAL_P3_01_H (REG_HDCP_DUAL_P3_BASE + 0x03)
5493 #define REG_HDCP_DUAL_P3_02_L (REG_HDCP_DUAL_P3_BASE + 0x04)
5494 #define REG_HDCP_DUAL_P3_02_H (REG_HDCP_DUAL_P3_BASE + 0x05)
5495 #define REG_HDCP_DUAL_P3_03_L (REG_HDCP_DUAL_P3_BASE + 0x06)
5496 #define REG_HDCP_DUAL_P3_03_H (REG_HDCP_DUAL_P3_BASE + 0x07)
5497 #define REG_HDCP_DUAL_P3_04_L (REG_HDCP_DUAL_P3_BASE + 0x08)
5498 #define REG_HDCP_DUAL_P3_04_H (REG_HDCP_DUAL_P3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h586 #define REG_HDCP_DUAL_P3_BASE 0x171B00UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h5489 #define REG_HDCP_DUAL_P3_00_L (REG_HDCP_DUAL_P3_BASE + 0x00)
5490 #define REG_HDCP_DUAL_P3_00_H (REG_HDCP_DUAL_P3_BASE + 0x01)
5491 #define REG_HDCP_DUAL_P3_01_L (REG_HDCP_DUAL_P3_BASE + 0x02)
5492 #define REG_HDCP_DUAL_P3_01_H (REG_HDCP_DUAL_P3_BASE + 0x03)
5493 #define REG_HDCP_DUAL_P3_02_L (REG_HDCP_DUAL_P3_BASE + 0x04)
5494 #define REG_HDCP_DUAL_P3_02_H (REG_HDCP_DUAL_P3_BASE + 0x05)
5495 #define REG_HDCP_DUAL_P3_03_L (REG_HDCP_DUAL_P3_BASE + 0x06)
5496 #define REG_HDCP_DUAL_P3_03_H (REG_HDCP_DUAL_P3_BASE + 0x07)
5497 #define REG_HDCP_DUAL_P3_04_L (REG_HDCP_DUAL_P3_BASE + 0x08)
5498 #define REG_HDCP_DUAL_P3_04_H (REG_HDCP_DUAL_P3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h557 #define REG_HDCP_DUAL_P3_BASE 0x171B00UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h5490 #define REG_HDCP_DUAL_P3_00_L (REG_HDCP_DUAL_P3_BASE + 0x00)
5491 #define REG_HDCP_DUAL_P3_00_H (REG_HDCP_DUAL_P3_BASE + 0x01)
5492 #define REG_HDCP_DUAL_P3_01_L (REG_HDCP_DUAL_P3_BASE + 0x02)
5493 #define REG_HDCP_DUAL_P3_01_H (REG_HDCP_DUAL_P3_BASE + 0x03)
5494 #define REG_HDCP_DUAL_P3_02_L (REG_HDCP_DUAL_P3_BASE + 0x04)
5495 #define REG_HDCP_DUAL_P3_02_H (REG_HDCP_DUAL_P3_BASE + 0x05)
5496 #define REG_HDCP_DUAL_P3_03_L (REG_HDCP_DUAL_P3_BASE + 0x06)
5497 #define REG_HDCP_DUAL_P3_03_H (REG_HDCP_DUAL_P3_BASE + 0x07)
5498 #define REG_HDCP_DUAL_P3_04_L (REG_HDCP_DUAL_P3_BASE + 0x08)
5499 #define REG_HDCP_DUAL_P3_04_H (REG_HDCP_DUAL_P3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h540 #define REG_HDCP_DUAL_P3_BASE 0x171B00UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h5495 #define REG_HDCP_DUAL_P3_00_L (REG_HDCP_DUAL_P3_BASE + 0x00)
5496 #define REG_HDCP_DUAL_P3_00_H (REG_HDCP_DUAL_P3_BASE + 0x01)
5497 #define REG_HDCP_DUAL_P3_01_L (REG_HDCP_DUAL_P3_BASE + 0x02)
5498 #define REG_HDCP_DUAL_P3_01_H (REG_HDCP_DUAL_P3_BASE + 0x03)
5499 #define REG_HDCP_DUAL_P3_02_L (REG_HDCP_DUAL_P3_BASE + 0x04)
5500 #define REG_HDCP_DUAL_P3_02_H (REG_HDCP_DUAL_P3_BASE + 0x05)
5501 #define REG_HDCP_DUAL_P3_03_L (REG_HDCP_DUAL_P3_BASE + 0x06)
5502 #define REG_HDCP_DUAL_P3_03_H (REG_HDCP_DUAL_P3_BASE + 0x07)
5503 #define REG_HDCP_DUAL_P3_04_L (REG_HDCP_DUAL_P3_BASE + 0x08)
5504 #define REG_HDCP_DUAL_P3_04_H (REG_HDCP_DUAL_P3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h645 #define REG_HDCP_DUAL_P3_BASE 0x171B00UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h5495 #define REG_HDCP_DUAL_P3_00_L (REG_HDCP_DUAL_P3_BASE + 0x00)
5496 #define REG_HDCP_DUAL_P3_00_H (REG_HDCP_DUAL_P3_BASE + 0x01)
5497 #define REG_HDCP_DUAL_P3_01_L (REG_HDCP_DUAL_P3_BASE + 0x02)
5498 #define REG_HDCP_DUAL_P3_01_H (REG_HDCP_DUAL_P3_BASE + 0x03)
5499 #define REG_HDCP_DUAL_P3_02_L (REG_HDCP_DUAL_P3_BASE + 0x04)
5500 #define REG_HDCP_DUAL_P3_02_H (REG_HDCP_DUAL_P3_BASE + 0x05)
5501 #define REG_HDCP_DUAL_P3_03_L (REG_HDCP_DUAL_P3_BASE + 0x06)
5502 #define REG_HDCP_DUAL_P3_03_H (REG_HDCP_DUAL_P3_BASE + 0x07)
5503 #define REG_HDCP_DUAL_P3_04_L (REG_HDCP_DUAL_P3_BASE + 0x08)
5504 #define REG_HDCP_DUAL_P3_04_H (REG_HDCP_DUAL_P3_BASE + 0x09)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_hdmi.h5495 #define REG_HDCP_DUAL_P3_00_L (REG_HDCP_DUAL_P3_BASE + 0x00)
5496 #define REG_HDCP_DUAL_P3_00_H (REG_HDCP_DUAL_P3_BASE + 0x01)
5497 #define REG_HDCP_DUAL_P3_01_L (REG_HDCP_DUAL_P3_BASE + 0x02)
5498 #define REG_HDCP_DUAL_P3_01_H (REG_HDCP_DUAL_P3_BASE + 0x03)
5499 #define REG_HDCP_DUAL_P3_02_L (REG_HDCP_DUAL_P3_BASE + 0x04)
5500 #define REG_HDCP_DUAL_P3_02_H (REG_HDCP_DUAL_P3_BASE + 0x05)
5501 #define REG_HDCP_DUAL_P3_03_L (REG_HDCP_DUAL_P3_BASE + 0x06)
5502 #define REG_HDCP_DUAL_P3_03_H (REG_HDCP_DUAL_P3_BASE + 0x07)
5503 #define REG_HDCP_DUAL_P3_04_L (REG_HDCP_DUAL_P3_BASE + 0x08)
5504 #define REG_HDCP_DUAL_P3_04_H (REG_HDCP_DUAL_P3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h650 #define REG_HDCP_DUAL_P3_BASE 0x171B00UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h5489 #define REG_HDCP_DUAL_P3_00_L (REG_HDCP_DUAL_P3_BASE + 0x00)
5490 #define REG_HDCP_DUAL_P3_00_H (REG_HDCP_DUAL_P3_BASE + 0x01)
5491 #define REG_HDCP_DUAL_P3_01_L (REG_HDCP_DUAL_P3_BASE + 0x02)
5492 #define REG_HDCP_DUAL_P3_01_H (REG_HDCP_DUAL_P3_BASE + 0x03)
5493 #define REG_HDCP_DUAL_P3_02_L (REG_HDCP_DUAL_P3_BASE + 0x04)
5494 #define REG_HDCP_DUAL_P3_02_H (REG_HDCP_DUAL_P3_BASE + 0x05)
5495 #define REG_HDCP_DUAL_P3_03_L (REG_HDCP_DUAL_P3_BASE + 0x06)
5496 #define REG_HDCP_DUAL_P3_03_H (REG_HDCP_DUAL_P3_BASE + 0x07)
5497 #define REG_HDCP_DUAL_P3_04_L (REG_HDCP_DUAL_P3_BASE + 0x08)
5498 #define REG_HDCP_DUAL_P3_04_H (REG_HDCP_DUAL_P3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h633 #define REG_HDCP_DUAL_P3_BASE 0x171B00UL macro

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