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Searched refs:REG_HDCP_DUAL_P2_BASE (Results 1 – 25 of 27) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h4959 #define REG_HDCP_DUAL_P2_00_L (REG_HDCP_DUAL_P2_BASE + 0x00)
4960 #define REG_HDCP_DUAL_P2_00_H (REG_HDCP_DUAL_P2_BASE + 0x01)
4961 #define REG_HDCP_DUAL_P2_01_L (REG_HDCP_DUAL_P2_BASE + 0x02)
4962 #define REG_HDCP_DUAL_P2_01_H (REG_HDCP_DUAL_P2_BASE + 0x03)
4963 #define REG_HDCP_DUAL_P2_02_L (REG_HDCP_DUAL_P2_BASE + 0x04)
4964 #define REG_HDCP_DUAL_P2_02_H (REG_HDCP_DUAL_P2_BASE + 0x05)
4965 #define REG_HDCP_DUAL_P2_03_L (REG_HDCP_DUAL_P2_BASE + 0x06)
4966 #define REG_HDCP_DUAL_P2_03_H (REG_HDCP_DUAL_P2_BASE + 0x07)
4967 #define REG_HDCP_DUAL_P2_04_L (REG_HDCP_DUAL_P2_BASE + 0x08)
4968 #define REG_HDCP_DUAL_P2_04_H (REG_HDCP_DUAL_P2_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h596 #define REG_HDCP_DUAL_P2_BASE 0x171800UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h4961 #define REG_HDCP_DUAL_P2_00_L (REG_HDCP_DUAL_P2_BASE + 0x00)
4962 #define REG_HDCP_DUAL_P2_00_H (REG_HDCP_DUAL_P2_BASE + 0x01)
4963 #define REG_HDCP_DUAL_P2_01_L (REG_HDCP_DUAL_P2_BASE + 0x02)
4964 #define REG_HDCP_DUAL_P2_01_H (REG_HDCP_DUAL_P2_BASE + 0x03)
4965 #define REG_HDCP_DUAL_P2_02_L (REG_HDCP_DUAL_P2_BASE + 0x04)
4966 #define REG_HDCP_DUAL_P2_02_H (REG_HDCP_DUAL_P2_BASE + 0x05)
4967 #define REG_HDCP_DUAL_P2_03_L (REG_HDCP_DUAL_P2_BASE + 0x06)
4968 #define REG_HDCP_DUAL_P2_03_H (REG_HDCP_DUAL_P2_BASE + 0x07)
4969 #define REG_HDCP_DUAL_P2_04_L (REG_HDCP_DUAL_P2_BASE + 0x08)
4970 #define REG_HDCP_DUAL_P2_04_H (REG_HDCP_DUAL_P2_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h578 #define REG_HDCP_DUAL_P2_BASE REG_HDCP_DUAL_P0_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h4961 #define REG_HDCP_DUAL_P2_00_L (REG_HDCP_DUAL_P2_BASE + 0x00)
4962 #define REG_HDCP_DUAL_P2_00_H (REG_HDCP_DUAL_P2_BASE + 0x01)
4963 #define REG_HDCP_DUAL_P2_01_L (REG_HDCP_DUAL_P2_BASE + 0x02)
4964 #define REG_HDCP_DUAL_P2_01_H (REG_HDCP_DUAL_P2_BASE + 0x03)
4965 #define REG_HDCP_DUAL_P2_02_L (REG_HDCP_DUAL_P2_BASE + 0x04)
4966 #define REG_HDCP_DUAL_P2_02_H (REG_HDCP_DUAL_P2_BASE + 0x05)
4967 #define REG_HDCP_DUAL_P2_03_L (REG_HDCP_DUAL_P2_BASE + 0x06)
4968 #define REG_HDCP_DUAL_P2_03_H (REG_HDCP_DUAL_P2_BASE + 0x07)
4969 #define REG_HDCP_DUAL_P2_04_L (REG_HDCP_DUAL_P2_BASE + 0x08)
4970 #define REG_HDCP_DUAL_P2_04_H (REG_HDCP_DUAL_P2_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h580 #define REG_HDCP_DUAL_P2_BASE REG_HDCP_DUAL_P0_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h4961 #define REG_HDCP_DUAL_P2_00_L (REG_HDCP_DUAL_P2_BASE + 0x00)
4962 #define REG_HDCP_DUAL_P2_00_H (REG_HDCP_DUAL_P2_BASE + 0x01)
4963 #define REG_HDCP_DUAL_P2_01_L (REG_HDCP_DUAL_P2_BASE + 0x02)
4964 #define REG_HDCP_DUAL_P2_01_H (REG_HDCP_DUAL_P2_BASE + 0x03)
4965 #define REG_HDCP_DUAL_P2_02_L (REG_HDCP_DUAL_P2_BASE + 0x04)
4966 #define REG_HDCP_DUAL_P2_02_H (REG_HDCP_DUAL_P2_BASE + 0x05)
4967 #define REG_HDCP_DUAL_P2_03_L (REG_HDCP_DUAL_P2_BASE + 0x06)
4968 #define REG_HDCP_DUAL_P2_03_H (REG_HDCP_DUAL_P2_BASE + 0x07)
4969 #define REG_HDCP_DUAL_P2_04_L (REG_HDCP_DUAL_P2_BASE + 0x08)
4970 #define REG_HDCP_DUAL_P2_04_H (REG_HDCP_DUAL_P2_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h572 #define REG_HDCP_DUAL_P2_BASE REG_HDCP_DUAL_P0_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h4961 #define REG_HDCP_DUAL_P2_00_L (REG_HDCP_DUAL_P2_BASE + 0x00)
4962 #define REG_HDCP_DUAL_P2_00_H (REG_HDCP_DUAL_P2_BASE + 0x01)
4963 #define REG_HDCP_DUAL_P2_01_L (REG_HDCP_DUAL_P2_BASE + 0x02)
4964 #define REG_HDCP_DUAL_P2_01_H (REG_HDCP_DUAL_P2_BASE + 0x03)
4965 #define REG_HDCP_DUAL_P2_02_L (REG_HDCP_DUAL_P2_BASE + 0x04)
4966 #define REG_HDCP_DUAL_P2_02_H (REG_HDCP_DUAL_P2_BASE + 0x05)
4967 #define REG_HDCP_DUAL_P2_03_L (REG_HDCP_DUAL_P2_BASE + 0x06)
4968 #define REG_HDCP_DUAL_P2_03_H (REG_HDCP_DUAL_P2_BASE + 0x07)
4969 #define REG_HDCP_DUAL_P2_04_L (REG_HDCP_DUAL_P2_BASE + 0x08)
4970 #define REG_HDCP_DUAL_P2_04_H (REG_HDCP_DUAL_P2_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h578 #define REG_HDCP_DUAL_P2_BASE REG_HDCP_DUAL_P0_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h4955 #define REG_HDCP_DUAL_P2_00_L (REG_HDCP_DUAL_P2_BASE + 0x00)
4956 #define REG_HDCP_DUAL_P2_00_H (REG_HDCP_DUAL_P2_BASE + 0x01)
4957 #define REG_HDCP_DUAL_P2_01_L (REG_HDCP_DUAL_P2_BASE + 0x02)
4958 #define REG_HDCP_DUAL_P2_01_H (REG_HDCP_DUAL_P2_BASE + 0x03)
4959 #define REG_HDCP_DUAL_P2_02_L (REG_HDCP_DUAL_P2_BASE + 0x04)
4960 #define REG_HDCP_DUAL_P2_02_H (REG_HDCP_DUAL_P2_BASE + 0x05)
4961 #define REG_HDCP_DUAL_P2_03_L (REG_HDCP_DUAL_P2_BASE + 0x06)
4962 #define REG_HDCP_DUAL_P2_03_H (REG_HDCP_DUAL_P2_BASE + 0x07)
4963 #define REG_HDCP_DUAL_P2_04_L (REG_HDCP_DUAL_P2_BASE + 0x08)
4964 #define REG_HDCP_DUAL_P2_04_H (REG_HDCP_DUAL_P2_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h556 #define REG_HDCP_DUAL_P2_BASE 0x171800UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h4955 #define REG_HDCP_DUAL_P2_00_L (REG_HDCP_DUAL_P2_BASE + 0x00)
4956 #define REG_HDCP_DUAL_P2_00_H (REG_HDCP_DUAL_P2_BASE + 0x01)
4957 #define REG_HDCP_DUAL_P2_01_L (REG_HDCP_DUAL_P2_BASE + 0x02)
4958 #define REG_HDCP_DUAL_P2_01_H (REG_HDCP_DUAL_P2_BASE + 0x03)
4959 #define REG_HDCP_DUAL_P2_02_L (REG_HDCP_DUAL_P2_BASE + 0x04)
4960 #define REG_HDCP_DUAL_P2_02_H (REG_HDCP_DUAL_P2_BASE + 0x05)
4961 #define REG_HDCP_DUAL_P2_03_L (REG_HDCP_DUAL_P2_BASE + 0x06)
4962 #define REG_HDCP_DUAL_P2_03_H (REG_HDCP_DUAL_P2_BASE + 0x07)
4963 #define REG_HDCP_DUAL_P2_04_L (REG_HDCP_DUAL_P2_BASE + 0x08)
4964 #define REG_HDCP_DUAL_P2_04_H (REG_HDCP_DUAL_P2_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h583 #define REG_HDCP_DUAL_P2_BASE 0x171800UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h4955 #define REG_HDCP_DUAL_P2_00_L (REG_HDCP_DUAL_P2_BASE + 0x00)
4956 #define REG_HDCP_DUAL_P2_00_H (REG_HDCP_DUAL_P2_BASE + 0x01)
4957 #define REG_HDCP_DUAL_P2_01_L (REG_HDCP_DUAL_P2_BASE + 0x02)
4958 #define REG_HDCP_DUAL_P2_01_H (REG_HDCP_DUAL_P2_BASE + 0x03)
4959 #define REG_HDCP_DUAL_P2_02_L (REG_HDCP_DUAL_P2_BASE + 0x04)
4960 #define REG_HDCP_DUAL_P2_02_H (REG_HDCP_DUAL_P2_BASE + 0x05)
4961 #define REG_HDCP_DUAL_P2_03_L (REG_HDCP_DUAL_P2_BASE + 0x06)
4962 #define REG_HDCP_DUAL_P2_03_H (REG_HDCP_DUAL_P2_BASE + 0x07)
4963 #define REG_HDCP_DUAL_P2_04_L (REG_HDCP_DUAL_P2_BASE + 0x08)
4964 #define REG_HDCP_DUAL_P2_04_H (REG_HDCP_DUAL_P2_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h554 #define REG_HDCP_DUAL_P2_BASE 0x171800UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h4956 #define REG_HDCP_DUAL_P2_00_L (REG_HDCP_DUAL_P2_BASE + 0x00)
4957 #define REG_HDCP_DUAL_P2_00_H (REG_HDCP_DUAL_P2_BASE + 0x01)
4958 #define REG_HDCP_DUAL_P2_01_L (REG_HDCP_DUAL_P2_BASE + 0x02)
4959 #define REG_HDCP_DUAL_P2_01_H (REG_HDCP_DUAL_P2_BASE + 0x03)
4960 #define REG_HDCP_DUAL_P2_02_L (REG_HDCP_DUAL_P2_BASE + 0x04)
4961 #define REG_HDCP_DUAL_P2_02_H (REG_HDCP_DUAL_P2_BASE + 0x05)
4962 #define REG_HDCP_DUAL_P2_03_L (REG_HDCP_DUAL_P2_BASE + 0x06)
4963 #define REG_HDCP_DUAL_P2_03_H (REG_HDCP_DUAL_P2_BASE + 0x07)
4964 #define REG_HDCP_DUAL_P2_04_L (REG_HDCP_DUAL_P2_BASE + 0x08)
4965 #define REG_HDCP_DUAL_P2_04_H (REG_HDCP_DUAL_P2_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h537 #define REG_HDCP_DUAL_P2_BASE 0x171800UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h4959 #define REG_HDCP_DUAL_P2_00_L (REG_HDCP_DUAL_P2_BASE + 0x00)
4960 #define REG_HDCP_DUAL_P2_00_H (REG_HDCP_DUAL_P2_BASE + 0x01)
4961 #define REG_HDCP_DUAL_P2_01_L (REG_HDCP_DUAL_P2_BASE + 0x02)
4962 #define REG_HDCP_DUAL_P2_01_H (REG_HDCP_DUAL_P2_BASE + 0x03)
4963 #define REG_HDCP_DUAL_P2_02_L (REG_HDCP_DUAL_P2_BASE + 0x04)
4964 #define REG_HDCP_DUAL_P2_02_H (REG_HDCP_DUAL_P2_BASE + 0x05)
4965 #define REG_HDCP_DUAL_P2_03_L (REG_HDCP_DUAL_P2_BASE + 0x06)
4966 #define REG_HDCP_DUAL_P2_03_H (REG_HDCP_DUAL_P2_BASE + 0x07)
4967 #define REG_HDCP_DUAL_P2_04_L (REG_HDCP_DUAL_P2_BASE + 0x08)
4968 #define REG_HDCP_DUAL_P2_04_H (REG_HDCP_DUAL_P2_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h642 #define REG_HDCP_DUAL_P2_BASE 0x171800UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h4959 #define REG_HDCP_DUAL_P2_00_L (REG_HDCP_DUAL_P2_BASE + 0x00)
4960 #define REG_HDCP_DUAL_P2_00_H (REG_HDCP_DUAL_P2_BASE + 0x01)
4961 #define REG_HDCP_DUAL_P2_01_L (REG_HDCP_DUAL_P2_BASE + 0x02)
4962 #define REG_HDCP_DUAL_P2_01_H (REG_HDCP_DUAL_P2_BASE + 0x03)
4963 #define REG_HDCP_DUAL_P2_02_L (REG_HDCP_DUAL_P2_BASE + 0x04)
4964 #define REG_HDCP_DUAL_P2_02_H (REG_HDCP_DUAL_P2_BASE + 0x05)
4965 #define REG_HDCP_DUAL_P2_03_L (REG_HDCP_DUAL_P2_BASE + 0x06)
4966 #define REG_HDCP_DUAL_P2_03_H (REG_HDCP_DUAL_P2_BASE + 0x07)
4967 #define REG_HDCP_DUAL_P2_04_L (REG_HDCP_DUAL_P2_BASE + 0x08)
4968 #define REG_HDCP_DUAL_P2_04_H (REG_HDCP_DUAL_P2_BASE + 0x09)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_hdmi.h4959 #define REG_HDCP_DUAL_P2_00_L (REG_HDCP_DUAL_P2_BASE + 0x00)
4960 #define REG_HDCP_DUAL_P2_00_H (REG_HDCP_DUAL_P2_BASE + 0x01)
4961 #define REG_HDCP_DUAL_P2_01_L (REG_HDCP_DUAL_P2_BASE + 0x02)
4962 #define REG_HDCP_DUAL_P2_01_H (REG_HDCP_DUAL_P2_BASE + 0x03)
4963 #define REG_HDCP_DUAL_P2_02_L (REG_HDCP_DUAL_P2_BASE + 0x04)
4964 #define REG_HDCP_DUAL_P2_02_H (REG_HDCP_DUAL_P2_BASE + 0x05)
4965 #define REG_HDCP_DUAL_P2_03_L (REG_HDCP_DUAL_P2_BASE + 0x06)
4966 #define REG_HDCP_DUAL_P2_03_H (REG_HDCP_DUAL_P2_BASE + 0x07)
4967 #define REG_HDCP_DUAL_P2_04_L (REG_HDCP_DUAL_P2_BASE + 0x08)
4968 #define REG_HDCP_DUAL_P2_04_H (REG_HDCP_DUAL_P2_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h647 #define REG_HDCP_DUAL_P2_BASE 0x171800UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h4955 #define REG_HDCP_DUAL_P2_00_L (REG_HDCP_DUAL_P2_BASE + 0x00)
4956 #define REG_HDCP_DUAL_P2_00_H (REG_HDCP_DUAL_P2_BASE + 0x01)
4957 #define REG_HDCP_DUAL_P2_01_L (REG_HDCP_DUAL_P2_BASE + 0x02)
4958 #define REG_HDCP_DUAL_P2_01_H (REG_HDCP_DUAL_P2_BASE + 0x03)
4959 #define REG_HDCP_DUAL_P2_02_L (REG_HDCP_DUAL_P2_BASE + 0x04)
4960 #define REG_HDCP_DUAL_P2_02_H (REG_HDCP_DUAL_P2_BASE + 0x05)
4961 #define REG_HDCP_DUAL_P2_03_L (REG_HDCP_DUAL_P2_BASE + 0x06)
4962 #define REG_HDCP_DUAL_P2_03_H (REG_HDCP_DUAL_P2_BASE + 0x07)
4963 #define REG_HDCP_DUAL_P2_04_L (REG_HDCP_DUAL_P2_BASE + 0x08)
4964 #define REG_HDCP_DUAL_P2_04_H (REG_HDCP_DUAL_P2_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h630 #define REG_HDCP_DUAL_P2_BASE 0x171800UL macro

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