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Searched refs:REG_HDCP_DUAL_P1_BASE (Results 1 – 25 of 27) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h4423 #define REG_HDCP_DUAL_P1_00_L (REG_HDCP_DUAL_P1_BASE + 0x00)
4424 #define REG_HDCP_DUAL_P1_00_H (REG_HDCP_DUAL_P1_BASE + 0x01)
4425 #define REG_HDCP_DUAL_P1_01_L (REG_HDCP_DUAL_P1_BASE + 0x02)
4426 #define REG_HDCP_DUAL_P1_01_H (REG_HDCP_DUAL_P1_BASE + 0x03)
4427 #define REG_HDCP_DUAL_P1_02_L (REG_HDCP_DUAL_P1_BASE + 0x04)
4428 #define REG_HDCP_DUAL_P1_02_H (REG_HDCP_DUAL_P1_BASE + 0x05)
4429 #define REG_HDCP_DUAL_P1_03_L (REG_HDCP_DUAL_P1_BASE + 0x06)
4430 #define REG_HDCP_DUAL_P1_03_H (REG_HDCP_DUAL_P1_BASE + 0x07)
4431 #define REG_HDCP_DUAL_P1_04_L (REG_HDCP_DUAL_P1_BASE + 0x08)
4432 #define REG_HDCP_DUAL_P1_04_H (REG_HDCP_DUAL_P1_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h593 #define REG_HDCP_DUAL_P1_BASE 0x171500UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h4425 #define REG_HDCP_DUAL_P1_00_L (REG_HDCP_DUAL_P1_BASE + 0x00)
4426 #define REG_HDCP_DUAL_P1_00_H (REG_HDCP_DUAL_P1_BASE + 0x01)
4427 #define REG_HDCP_DUAL_P1_01_L (REG_HDCP_DUAL_P1_BASE + 0x02)
4428 #define REG_HDCP_DUAL_P1_01_H (REG_HDCP_DUAL_P1_BASE + 0x03)
4429 #define REG_HDCP_DUAL_P1_02_L (REG_HDCP_DUAL_P1_BASE + 0x04)
4430 #define REG_HDCP_DUAL_P1_02_H (REG_HDCP_DUAL_P1_BASE + 0x05)
4431 #define REG_HDCP_DUAL_P1_03_L (REG_HDCP_DUAL_P1_BASE + 0x06)
4432 #define REG_HDCP_DUAL_P1_03_H (REG_HDCP_DUAL_P1_BASE + 0x07)
4433 #define REG_HDCP_DUAL_P1_04_L (REG_HDCP_DUAL_P1_BASE + 0x08)
4434 #define REG_HDCP_DUAL_P1_04_H (REG_HDCP_DUAL_P1_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h575 #define REG_HDCP_DUAL_P1_BASE REG_HDCP_DUAL_P0_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h4425 #define REG_HDCP_DUAL_P1_00_L (REG_HDCP_DUAL_P1_BASE + 0x00)
4426 #define REG_HDCP_DUAL_P1_00_H (REG_HDCP_DUAL_P1_BASE + 0x01)
4427 #define REG_HDCP_DUAL_P1_01_L (REG_HDCP_DUAL_P1_BASE + 0x02)
4428 #define REG_HDCP_DUAL_P1_01_H (REG_HDCP_DUAL_P1_BASE + 0x03)
4429 #define REG_HDCP_DUAL_P1_02_L (REG_HDCP_DUAL_P1_BASE + 0x04)
4430 #define REG_HDCP_DUAL_P1_02_H (REG_HDCP_DUAL_P1_BASE + 0x05)
4431 #define REG_HDCP_DUAL_P1_03_L (REG_HDCP_DUAL_P1_BASE + 0x06)
4432 #define REG_HDCP_DUAL_P1_03_H (REG_HDCP_DUAL_P1_BASE + 0x07)
4433 #define REG_HDCP_DUAL_P1_04_L (REG_HDCP_DUAL_P1_BASE + 0x08)
4434 #define REG_HDCP_DUAL_P1_04_H (REG_HDCP_DUAL_P1_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h577 #define REG_HDCP_DUAL_P1_BASE REG_HDCP_DUAL_P0_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h4425 #define REG_HDCP_DUAL_P1_00_L (REG_HDCP_DUAL_P1_BASE + 0x00)
4426 #define REG_HDCP_DUAL_P1_00_H (REG_HDCP_DUAL_P1_BASE + 0x01)
4427 #define REG_HDCP_DUAL_P1_01_L (REG_HDCP_DUAL_P1_BASE + 0x02)
4428 #define REG_HDCP_DUAL_P1_01_H (REG_HDCP_DUAL_P1_BASE + 0x03)
4429 #define REG_HDCP_DUAL_P1_02_L (REG_HDCP_DUAL_P1_BASE + 0x04)
4430 #define REG_HDCP_DUAL_P1_02_H (REG_HDCP_DUAL_P1_BASE + 0x05)
4431 #define REG_HDCP_DUAL_P1_03_L (REG_HDCP_DUAL_P1_BASE + 0x06)
4432 #define REG_HDCP_DUAL_P1_03_H (REG_HDCP_DUAL_P1_BASE + 0x07)
4433 #define REG_HDCP_DUAL_P1_04_L (REG_HDCP_DUAL_P1_BASE + 0x08)
4434 #define REG_HDCP_DUAL_P1_04_H (REG_HDCP_DUAL_P1_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h569 #define REG_HDCP_DUAL_P1_BASE REG_HDCP_DUAL_P0_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h4425 #define REG_HDCP_DUAL_P1_00_L (REG_HDCP_DUAL_P1_BASE + 0x00)
4426 #define REG_HDCP_DUAL_P1_00_H (REG_HDCP_DUAL_P1_BASE + 0x01)
4427 #define REG_HDCP_DUAL_P1_01_L (REG_HDCP_DUAL_P1_BASE + 0x02)
4428 #define REG_HDCP_DUAL_P1_01_H (REG_HDCP_DUAL_P1_BASE + 0x03)
4429 #define REG_HDCP_DUAL_P1_02_L (REG_HDCP_DUAL_P1_BASE + 0x04)
4430 #define REG_HDCP_DUAL_P1_02_H (REG_HDCP_DUAL_P1_BASE + 0x05)
4431 #define REG_HDCP_DUAL_P1_03_L (REG_HDCP_DUAL_P1_BASE + 0x06)
4432 #define REG_HDCP_DUAL_P1_03_H (REG_HDCP_DUAL_P1_BASE + 0x07)
4433 #define REG_HDCP_DUAL_P1_04_L (REG_HDCP_DUAL_P1_BASE + 0x08)
4434 #define REG_HDCP_DUAL_P1_04_H (REG_HDCP_DUAL_P1_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h575 #define REG_HDCP_DUAL_P1_BASE REG_HDCP_DUAL_P0_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h4421 #define REG_HDCP_DUAL_P1_00_L (REG_HDCP_DUAL_P1_BASE + 0x00)
4422 #define REG_HDCP_DUAL_P1_00_H (REG_HDCP_DUAL_P1_BASE + 0x01)
4423 #define REG_HDCP_DUAL_P1_01_L (REG_HDCP_DUAL_P1_BASE + 0x02)
4424 #define REG_HDCP_DUAL_P1_01_H (REG_HDCP_DUAL_P1_BASE + 0x03)
4425 #define REG_HDCP_DUAL_P1_02_L (REG_HDCP_DUAL_P1_BASE + 0x04)
4426 #define REG_HDCP_DUAL_P1_02_H (REG_HDCP_DUAL_P1_BASE + 0x05)
4427 #define REG_HDCP_DUAL_P1_03_L (REG_HDCP_DUAL_P1_BASE + 0x06)
4428 #define REG_HDCP_DUAL_P1_03_H (REG_HDCP_DUAL_P1_BASE + 0x07)
4429 #define REG_HDCP_DUAL_P1_04_L (REG_HDCP_DUAL_P1_BASE + 0x08)
4430 #define REG_HDCP_DUAL_P1_04_H (REG_HDCP_DUAL_P1_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h553 #define REG_HDCP_DUAL_P1_BASE 0x171500UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h4421 #define REG_HDCP_DUAL_P1_00_L (REG_HDCP_DUAL_P1_BASE + 0x00)
4422 #define REG_HDCP_DUAL_P1_00_H (REG_HDCP_DUAL_P1_BASE + 0x01)
4423 #define REG_HDCP_DUAL_P1_01_L (REG_HDCP_DUAL_P1_BASE + 0x02)
4424 #define REG_HDCP_DUAL_P1_01_H (REG_HDCP_DUAL_P1_BASE + 0x03)
4425 #define REG_HDCP_DUAL_P1_02_L (REG_HDCP_DUAL_P1_BASE + 0x04)
4426 #define REG_HDCP_DUAL_P1_02_H (REG_HDCP_DUAL_P1_BASE + 0x05)
4427 #define REG_HDCP_DUAL_P1_03_L (REG_HDCP_DUAL_P1_BASE + 0x06)
4428 #define REG_HDCP_DUAL_P1_03_H (REG_HDCP_DUAL_P1_BASE + 0x07)
4429 #define REG_HDCP_DUAL_P1_04_L (REG_HDCP_DUAL_P1_BASE + 0x08)
4430 #define REG_HDCP_DUAL_P1_04_H (REG_HDCP_DUAL_P1_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h580 #define REG_HDCP_DUAL_P1_BASE 0x171500UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h4421 #define REG_HDCP_DUAL_P1_00_L (REG_HDCP_DUAL_P1_BASE + 0x00)
4422 #define REG_HDCP_DUAL_P1_00_H (REG_HDCP_DUAL_P1_BASE + 0x01)
4423 #define REG_HDCP_DUAL_P1_01_L (REG_HDCP_DUAL_P1_BASE + 0x02)
4424 #define REG_HDCP_DUAL_P1_01_H (REG_HDCP_DUAL_P1_BASE + 0x03)
4425 #define REG_HDCP_DUAL_P1_02_L (REG_HDCP_DUAL_P1_BASE + 0x04)
4426 #define REG_HDCP_DUAL_P1_02_H (REG_HDCP_DUAL_P1_BASE + 0x05)
4427 #define REG_HDCP_DUAL_P1_03_L (REG_HDCP_DUAL_P1_BASE + 0x06)
4428 #define REG_HDCP_DUAL_P1_03_H (REG_HDCP_DUAL_P1_BASE + 0x07)
4429 #define REG_HDCP_DUAL_P1_04_L (REG_HDCP_DUAL_P1_BASE + 0x08)
4430 #define REG_HDCP_DUAL_P1_04_H (REG_HDCP_DUAL_P1_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h551 #define REG_HDCP_DUAL_P1_BASE 0x171500UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h4422 #define REG_HDCP_DUAL_P1_00_L (REG_HDCP_DUAL_P1_BASE + 0x00)
4423 #define REG_HDCP_DUAL_P1_00_H (REG_HDCP_DUAL_P1_BASE + 0x01)
4424 #define REG_HDCP_DUAL_P1_01_L (REG_HDCP_DUAL_P1_BASE + 0x02)
4425 #define REG_HDCP_DUAL_P1_01_H (REG_HDCP_DUAL_P1_BASE + 0x03)
4426 #define REG_HDCP_DUAL_P1_02_L (REG_HDCP_DUAL_P1_BASE + 0x04)
4427 #define REG_HDCP_DUAL_P1_02_H (REG_HDCP_DUAL_P1_BASE + 0x05)
4428 #define REG_HDCP_DUAL_P1_03_L (REG_HDCP_DUAL_P1_BASE + 0x06)
4429 #define REG_HDCP_DUAL_P1_03_H (REG_HDCP_DUAL_P1_BASE + 0x07)
4430 #define REG_HDCP_DUAL_P1_04_L (REG_HDCP_DUAL_P1_BASE + 0x08)
4431 #define REG_HDCP_DUAL_P1_04_H (REG_HDCP_DUAL_P1_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h534 #define REG_HDCP_DUAL_P1_BASE 0x171500UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h4423 #define REG_HDCP_DUAL_P1_00_L (REG_HDCP_DUAL_P1_BASE + 0x00)
4424 #define REG_HDCP_DUAL_P1_00_H (REG_HDCP_DUAL_P1_BASE + 0x01)
4425 #define REG_HDCP_DUAL_P1_01_L (REG_HDCP_DUAL_P1_BASE + 0x02)
4426 #define REG_HDCP_DUAL_P1_01_H (REG_HDCP_DUAL_P1_BASE + 0x03)
4427 #define REG_HDCP_DUAL_P1_02_L (REG_HDCP_DUAL_P1_BASE + 0x04)
4428 #define REG_HDCP_DUAL_P1_02_H (REG_HDCP_DUAL_P1_BASE + 0x05)
4429 #define REG_HDCP_DUAL_P1_03_L (REG_HDCP_DUAL_P1_BASE + 0x06)
4430 #define REG_HDCP_DUAL_P1_03_H (REG_HDCP_DUAL_P1_BASE + 0x07)
4431 #define REG_HDCP_DUAL_P1_04_L (REG_HDCP_DUAL_P1_BASE + 0x08)
4432 #define REG_HDCP_DUAL_P1_04_H (REG_HDCP_DUAL_P1_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h639 #define REG_HDCP_DUAL_P1_BASE 0x171500UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h4423 #define REG_HDCP_DUAL_P1_00_L (REG_HDCP_DUAL_P1_BASE + 0x00)
4424 #define REG_HDCP_DUAL_P1_00_H (REG_HDCP_DUAL_P1_BASE + 0x01)
4425 #define REG_HDCP_DUAL_P1_01_L (REG_HDCP_DUAL_P1_BASE + 0x02)
4426 #define REG_HDCP_DUAL_P1_01_H (REG_HDCP_DUAL_P1_BASE + 0x03)
4427 #define REG_HDCP_DUAL_P1_02_L (REG_HDCP_DUAL_P1_BASE + 0x04)
4428 #define REG_HDCP_DUAL_P1_02_H (REG_HDCP_DUAL_P1_BASE + 0x05)
4429 #define REG_HDCP_DUAL_P1_03_L (REG_HDCP_DUAL_P1_BASE + 0x06)
4430 #define REG_HDCP_DUAL_P1_03_H (REG_HDCP_DUAL_P1_BASE + 0x07)
4431 #define REG_HDCP_DUAL_P1_04_L (REG_HDCP_DUAL_P1_BASE + 0x08)
4432 #define REG_HDCP_DUAL_P1_04_H (REG_HDCP_DUAL_P1_BASE + 0x09)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_hdmi.h4423 #define REG_HDCP_DUAL_P1_00_L (REG_HDCP_DUAL_P1_BASE + 0x00)
4424 #define REG_HDCP_DUAL_P1_00_H (REG_HDCP_DUAL_P1_BASE + 0x01)
4425 #define REG_HDCP_DUAL_P1_01_L (REG_HDCP_DUAL_P1_BASE + 0x02)
4426 #define REG_HDCP_DUAL_P1_01_H (REG_HDCP_DUAL_P1_BASE + 0x03)
4427 #define REG_HDCP_DUAL_P1_02_L (REG_HDCP_DUAL_P1_BASE + 0x04)
4428 #define REG_HDCP_DUAL_P1_02_H (REG_HDCP_DUAL_P1_BASE + 0x05)
4429 #define REG_HDCP_DUAL_P1_03_L (REG_HDCP_DUAL_P1_BASE + 0x06)
4430 #define REG_HDCP_DUAL_P1_03_H (REG_HDCP_DUAL_P1_BASE + 0x07)
4431 #define REG_HDCP_DUAL_P1_04_L (REG_HDCP_DUAL_P1_BASE + 0x08)
4432 #define REG_HDCP_DUAL_P1_04_H (REG_HDCP_DUAL_P1_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h644 #define REG_HDCP_DUAL_P1_BASE 0x171500UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h4421 #define REG_HDCP_DUAL_P1_00_L (REG_HDCP_DUAL_P1_BASE + 0x00)
4422 #define REG_HDCP_DUAL_P1_00_H (REG_HDCP_DUAL_P1_BASE + 0x01)
4423 #define REG_HDCP_DUAL_P1_01_L (REG_HDCP_DUAL_P1_BASE + 0x02)
4424 #define REG_HDCP_DUAL_P1_01_H (REG_HDCP_DUAL_P1_BASE + 0x03)
4425 #define REG_HDCP_DUAL_P1_02_L (REG_HDCP_DUAL_P1_BASE + 0x04)
4426 #define REG_HDCP_DUAL_P1_02_H (REG_HDCP_DUAL_P1_BASE + 0x05)
4427 #define REG_HDCP_DUAL_P1_03_L (REG_HDCP_DUAL_P1_BASE + 0x06)
4428 #define REG_HDCP_DUAL_P1_03_H (REG_HDCP_DUAL_P1_BASE + 0x07)
4429 #define REG_HDCP_DUAL_P1_04_L (REG_HDCP_DUAL_P1_BASE + 0x08)
4430 #define REG_HDCP_DUAL_P1_04_H (REG_HDCP_DUAL_P1_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h627 #define REG_HDCP_DUAL_P1_BASE 0x171500UL macro

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