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Searched refs:REG_FIQ_MASK_H (Results 1 – 25 of 28) sorted by relevance

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/utopia/UTPA2-700.0.x/mxlib/hal/k7u/
H A DhalCHIP.c512 IRQ_REG(REG_FIQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
551 IRQ_REG(REG_FIQ_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQH_START)); in CHIP_EnableIRQ()
591 IRQ_REG(REG_FIQ_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
631 IRQ_REG(REG_FIQ_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQH_START)); in CHIP_DisableIRQ()
1648 IRQ_REG(REG_FIQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
1687 IRQ_REG(REG_FIQ_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQH_START)); in CHIP_EnableIRQ()
1727 IRQ_REG(REG_FIQ_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
1767 IRQ_REG(REG_FIQ_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQH_START)); in CHIP_DisableIRQ()
H A DregCHIP.h116 #define REG_FIQ_MASK_H 0x0025 macro
143 #define REG_FIQ_MASK_H (REG_INT_BASE_ADDR + 0x0005) macro
/utopia/UTPA2-700.0.x/mxlib/hal/k6lite/
H A DhalCHIP.c512 IRQ_REG(REG_FIQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
551 IRQ_REG(REG_FIQ_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQH_START)); in CHIP_EnableIRQ()
591 IRQ_REG(REG_FIQ_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
631 IRQ_REG(REG_FIQ_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQH_START)); in CHIP_DisableIRQ()
1648 IRQ_REG(REG_FIQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
1687 IRQ_REG(REG_FIQ_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQH_START)); in CHIP_EnableIRQ()
1727 IRQ_REG(REG_FIQ_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
1767 IRQ_REG(REG_FIQ_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQH_START)); in CHIP_DisableIRQ()
H A DregCHIP.h116 #define REG_FIQ_MASK_H 0x0025 macro
143 #define REG_FIQ_MASK_H (REG_INT_BASE_ADDR + 0x0005) macro
/utopia/UTPA2-700.0.x/mxlib/hal/curry/
H A DhalCHIP.c512 IRQ_REG(REG_FIQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
551 IRQ_REG(REG_FIQ_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQH_START)); in CHIP_EnableIRQ()
591 IRQ_REG(REG_FIQ_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
631 IRQ_REG(REG_FIQ_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQH_START)); in CHIP_DisableIRQ()
1635 IRQ_REG(REG_FIQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
1674 IRQ_REG(REG_FIQ_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQH_START)); in CHIP_EnableIRQ()
1714 IRQ_REG(REG_FIQ_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
1754 IRQ_REG(REG_FIQ_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQH_START)); in CHIP_DisableIRQ()
H A DregCHIP.h116 #define REG_FIQ_MASK_H 0x0025 macro
143 #define REG_FIQ_MASK_H (REG_INT_BASE_ADDR + 0x0005) macro
/utopia/UTPA2-700.0.x/mxlib/hal/kano/
H A DhalCHIP.c512 IRQ_REG(REG_FIQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
551 IRQ_REG(REG_FIQ_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQH_START)); in CHIP_EnableIRQ()
591 IRQ_REG(REG_FIQ_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
631 IRQ_REG(REG_FIQ_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQH_START)); in CHIP_DisableIRQ()
1648 IRQ_REG(REG_FIQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
1687 IRQ_REG(REG_FIQ_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQH_START)); in CHIP_EnableIRQ()
1727 IRQ_REG(REG_FIQ_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
1767 IRQ_REG(REG_FIQ_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQH_START)); in CHIP_DisableIRQ()
H A DregCHIP.h116 #define REG_FIQ_MASK_H 0x0025 macro
143 #define REG_FIQ_MASK_H (REG_INT_BASE_ADDR + 0x0005) macro
/utopia/UTPA2-700.0.x/mxlib/hal/k6/
H A DhalCHIP.c512 IRQ_REG(REG_FIQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
551 IRQ_REG(REG_FIQ_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQH_START)); in CHIP_EnableIRQ()
591 IRQ_REG(REG_FIQ_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
631 IRQ_REG(REG_FIQ_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQH_START)); in CHIP_DisableIRQ()
1648 IRQ_REG(REG_FIQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
1687 IRQ_REG(REG_FIQ_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQH_START)); in CHIP_EnableIRQ()
1727 IRQ_REG(REG_FIQ_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
1767 IRQ_REG(REG_FIQ_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQH_START)); in CHIP_DisableIRQ()
H A DregCHIP.h116 #define REG_FIQ_MASK_H 0x0025 macro
143 #define REG_FIQ_MASK_H (REG_INT_BASE_ADDR + 0x0005) macro
/utopia/UTPA2-700.0.x/mxlib/hal/M7821/
H A DhalCHIP.c444 IRQ_REG(REG_FIQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
470 IRQ_REG(REG_FIQ_MASK_H) &= ~(0x1 << (u8VectorIndex-E_FIQH_START) ); in CHIP_EnableIRQ()
503 IRQ_REG(REG_FIQ_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
530 IRQ_REG(REG_FIQ_MASK_H) |= (0x1 << (u8VectorIndex-E_FIQH_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h135 #define REG_FIQ_MASK_H 0x0025 macro
161 #define REG_FIQ_MASK_H 0x0025 macro
/utopia/UTPA2-700.0.x/mxlib/hal/maxim/
H A DhalCHIP.c444 IRQ_REG(REG_FIQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
470 IRQ_REG(REG_FIQ_MASK_H) &= ~(0x1 << (u8VectorIndex-E_FIQH_START) ); in CHIP_EnableIRQ()
503 IRQ_REG(REG_FIQ_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
530 IRQ_REG(REG_FIQ_MASK_H) |= (0x1 << (u8VectorIndex-E_FIQH_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h135 #define REG_FIQ_MASK_H 0x0025 macro
160 #define REG_FIQ_MASK_H 0x0025 macro
/utopia/UTPA2-700.0.x/mxlib/hal/marcus/
H A DhalCHIP.c444 IRQ_REG(REG_FIQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
470 IRQ_REG(REG_FIQ_MASK_H) &= ~(0x1 << (u8VectorIndex-E_FIQH_START) ); in CHIP_EnableIRQ()
503 IRQ_REG(REG_FIQ_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
530 IRQ_REG(REG_FIQ_MASK_H) |= (0x1 << (u8VectorIndex-E_FIQH_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h135 #define REG_FIQ_MASK_H 0x0025 macro
160 #define REG_FIQ_MASK_H 0x0025 macro
/utopia/UTPA2-700.0.x/mxlib/hal/mainz/
H A DhalCHIP.c427 IRQ_REG(REG_FIQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
453 IRQ_REG(REG_FIQ_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQH_START)); in CHIP_EnableIRQ()
485 IRQ_REG(REG_FIQ_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
512 IRQ_REG(REG_FIQ_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQH_START)); in CHIP_DisableIRQ()
/utopia/UTPA2-700.0.x/mxlib/hal/maserati/
H A DhalCHIP.c444 IRQ_REG(REG_FIQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
470 IRQ_REG(REG_FIQ_MASK_H) &= ~(0x1 << (u8VectorIndex-E_FIQH_START) ); in CHIP_EnableIRQ()
503 IRQ_REG(REG_FIQ_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
530 IRQ_REG(REG_FIQ_MASK_H) |= (0x1 << (u8VectorIndex-E_FIQH_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h135 #define REG_FIQ_MASK_H 0x0025 macro
160 #define REG_FIQ_MASK_H 0x0025 macro
/utopia/UTPA2-700.0.x/mxlib/hal/manhattan/
H A DhalCHIP.c444 IRQ_REG(REG_FIQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
470 IRQ_REG(REG_FIQ_MASK_H) &= ~(0x1 << (u8VectorIndex-E_FIQH_START) ); in CHIP_EnableIRQ()
503 IRQ_REG(REG_FIQ_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
530 IRQ_REG(REG_FIQ_MASK_H) |= (0x1 << (u8VectorIndex-E_FIQH_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h135 #define REG_FIQ_MASK_H 0x0025 macro
160 #define REG_FIQ_MASK_H 0x0025 macro
/utopia/UTPA2-700.0.x/mxlib/hal/mustang/
H A DhalCHIP.c427 IRQ_REG(REG_FIQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
453 IRQ_REG(REG_FIQ_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQH_START)); in CHIP_EnableIRQ()
485 IRQ_REG(REG_FIQ_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
512 IRQ_REG(REG_FIQ_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQH_START)); in CHIP_DisableIRQ()
/utopia/UTPA2-700.0.x/mxlib/hal/messi/
H A DhalCHIP.c427 IRQ_REG(REG_FIQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
453 IRQ_REG(REG_FIQ_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQH_START)); in CHIP_EnableIRQ()
485 IRQ_REG(REG_FIQ_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
512 IRQ_REG(REG_FIQ_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQH_START)); in CHIP_DisableIRQ()
/utopia/UTPA2-700.0.x/mxlib/hal/M7621/
H A DhalCHIP.c444 IRQ_REG(REG_FIQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
470 IRQ_REG(REG_FIQ_MASK_H) &= ~(0x1 << (u8VectorIndex-E_FIQH_START) ); in CHIP_EnableIRQ()
503 IRQ_REG(REG_FIQ_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
530 IRQ_REG(REG_FIQ_MASK_H) |= (0x1 << (u8VectorIndex-E_FIQH_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h135 #define REG_FIQ_MASK_H 0x0025 macro
161 #define REG_FIQ_MASK_H 0x0025 macro

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