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Searched refs:REG_FIQEXP_MASK_L (Results 1 – 25 of 28) sorted by relevance

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/utopia/UTPA2-700.0.x/mxlib/hal/k7u/
H A DhalCHIP.c513 IRQ_REG(REG_FIQEXP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
555 IRQ_REG(REG_FIQEXP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQEXPL_START)); in CHIP_EnableIRQ()
592 IRQ_REG(REG_FIQEXP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
636 IRQ_REG(REG_FIQEXP_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQEXPL_START)); in CHIP_DisableIRQ()
1649 IRQ_REG(REG_FIQEXP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
1691 IRQ_REG(REG_FIQEXP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQEXPL_START)); in CHIP_EnableIRQ()
1728 IRQ_REG(REG_FIQEXP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
1772 IRQ_REG(REG_FIQEXP_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQEXPL_START)); in CHIP_DisableIRQ()
H A DregCHIP.h117 #define REG_FIQEXP_MASK_L 0x0026 macro
144 #define REG_FIQEXP_MASK_L (REG_INT_BASE_ADDR + 0x0006) macro
/utopia/UTPA2-700.0.x/mxlib/hal/k6lite/
H A DhalCHIP.c513 IRQ_REG(REG_FIQEXP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
555 IRQ_REG(REG_FIQEXP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQEXPL_START)); in CHIP_EnableIRQ()
592 IRQ_REG(REG_FIQEXP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
636 IRQ_REG(REG_FIQEXP_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQEXPL_START)); in CHIP_DisableIRQ()
1649 IRQ_REG(REG_FIQEXP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
1691 IRQ_REG(REG_FIQEXP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQEXPL_START)); in CHIP_EnableIRQ()
1728 IRQ_REG(REG_FIQEXP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
1772 IRQ_REG(REG_FIQEXP_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQEXPL_START)); in CHIP_DisableIRQ()
H A DregCHIP.h117 #define REG_FIQEXP_MASK_L 0x0026 macro
144 #define REG_FIQEXP_MASK_L (REG_INT_BASE_ADDR + 0x0006) macro
/utopia/UTPA2-700.0.x/mxlib/hal/curry/
H A DhalCHIP.c513 IRQ_REG(REG_FIQEXP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
555 IRQ_REG(REG_FIQEXP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQEXPL_START)); in CHIP_EnableIRQ()
592 IRQ_REG(REG_FIQEXP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
636 IRQ_REG(REG_FIQEXP_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQEXPL_START)); in CHIP_DisableIRQ()
1636 IRQ_REG(REG_FIQEXP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
1678 IRQ_REG(REG_FIQEXP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQEXPL_START)); in CHIP_EnableIRQ()
1715 IRQ_REG(REG_FIQEXP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
1759 IRQ_REG(REG_FIQEXP_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQEXPL_START)); in CHIP_DisableIRQ()
H A DregCHIP.h117 #define REG_FIQEXP_MASK_L 0x0026 macro
144 #define REG_FIQEXP_MASK_L (REG_INT_BASE_ADDR + 0x0006) macro
/utopia/UTPA2-700.0.x/mxlib/hal/kano/
H A DhalCHIP.c513 IRQ_REG(REG_FIQEXP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
555 IRQ_REG(REG_FIQEXP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQEXPL_START)); in CHIP_EnableIRQ()
592 IRQ_REG(REG_FIQEXP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
636 IRQ_REG(REG_FIQEXP_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQEXPL_START)); in CHIP_DisableIRQ()
1649 IRQ_REG(REG_FIQEXP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
1691 IRQ_REG(REG_FIQEXP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQEXPL_START)); in CHIP_EnableIRQ()
1728 IRQ_REG(REG_FIQEXP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
1772 IRQ_REG(REG_FIQEXP_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQEXPL_START)); in CHIP_DisableIRQ()
H A DregCHIP.h117 #define REG_FIQEXP_MASK_L 0x0026 macro
144 #define REG_FIQEXP_MASK_L (REG_INT_BASE_ADDR + 0x0006) macro
/utopia/UTPA2-700.0.x/mxlib/hal/k6/
H A DhalCHIP.c513 IRQ_REG(REG_FIQEXP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
555 IRQ_REG(REG_FIQEXP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQEXPL_START)); in CHIP_EnableIRQ()
592 IRQ_REG(REG_FIQEXP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
636 IRQ_REG(REG_FIQEXP_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQEXPL_START)); in CHIP_DisableIRQ()
1649 IRQ_REG(REG_FIQEXP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
1691 IRQ_REG(REG_FIQEXP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQEXPL_START)); in CHIP_EnableIRQ()
1728 IRQ_REG(REG_FIQEXP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
1772 IRQ_REG(REG_FIQEXP_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQEXPL_START)); in CHIP_DisableIRQ()
H A DregCHIP.h117 #define REG_FIQEXP_MASK_L 0x0026 macro
144 #define REG_FIQEXP_MASK_L (REG_INT_BASE_ADDR + 0x0006) macro
/utopia/UTPA2-700.0.x/mxlib/hal/M7821/
H A DhalCHIP.c445 IRQ_REG(REG_FIQEXP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
474 IRQ_REG(REG_FIQEXP_MASK_L) &= ~(0x1 << (u8VectorIndex-E_FIQEXPL_START) ); in CHIP_EnableIRQ()
504 IRQ_REG(REG_FIQEXP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
535 IRQ_REG(REG_FIQEXP_MASK_L) |= (0x1 << (u8VectorIndex-E_FIQEXPL_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h136 #define REG_FIQEXP_MASK_L 0x0026 macro
162 #define REG_FIQEXP_MASK_L 0x0026 macro
/utopia/UTPA2-700.0.x/mxlib/hal/maxim/
H A DhalCHIP.c445 IRQ_REG(REG_FIQEXP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
474 IRQ_REG(REG_FIQEXP_MASK_L) &= ~(0x1 << (u8VectorIndex-E_FIQEXPL_START) ); in CHIP_EnableIRQ()
504 IRQ_REG(REG_FIQEXP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
535 IRQ_REG(REG_FIQEXP_MASK_L) |= (0x1 << (u8VectorIndex-E_FIQEXPL_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h136 #define REG_FIQEXP_MASK_L 0x0026 macro
161 #define REG_FIQEXP_MASK_L 0x0026 macro
/utopia/UTPA2-700.0.x/mxlib/hal/marcus/
H A DhalCHIP.c445 IRQ_REG(REG_FIQEXP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
474 IRQ_REG(REG_FIQEXP_MASK_L) &= ~(0x1 << (u8VectorIndex-E_FIQEXPL_START) ); in CHIP_EnableIRQ()
504 IRQ_REG(REG_FIQEXP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
535 IRQ_REG(REG_FIQEXP_MASK_L) |= (0x1 << (u8VectorIndex-E_FIQEXPL_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h136 #define REG_FIQEXP_MASK_L 0x0026 macro
161 #define REG_FIQEXP_MASK_L 0x0026 macro
/utopia/UTPA2-700.0.x/mxlib/hal/mainz/
H A DhalCHIP.c428 IRQ_REG(REG_FIQEXP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
457 IRQ_REG(REG_FIQEXP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQEXPL_START)); in CHIP_EnableIRQ()
486 IRQ_REG(REG_FIQEXP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
517 IRQ_REG(REG_FIQEXP_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQEXPL_START)); in CHIP_DisableIRQ()
/utopia/UTPA2-700.0.x/mxlib/hal/maserati/
H A DhalCHIP.c445 IRQ_REG(REG_FIQEXP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
474 IRQ_REG(REG_FIQEXP_MASK_L) &= ~(0x1 << (u8VectorIndex-E_FIQEXPL_START) ); in CHIP_EnableIRQ()
504 IRQ_REG(REG_FIQEXP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
535 IRQ_REG(REG_FIQEXP_MASK_L) |= (0x1 << (u8VectorIndex-E_FIQEXPL_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h136 #define REG_FIQEXP_MASK_L 0x0026 macro
161 #define REG_FIQEXP_MASK_L 0x0026 macro
/utopia/UTPA2-700.0.x/mxlib/hal/manhattan/
H A DhalCHIP.c445 IRQ_REG(REG_FIQEXP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
474 IRQ_REG(REG_FIQEXP_MASK_L) &= ~(0x1 << (u8VectorIndex-E_FIQEXPL_START) ); in CHIP_EnableIRQ()
504 IRQ_REG(REG_FIQEXP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
535 IRQ_REG(REG_FIQEXP_MASK_L) |= (0x1 << (u8VectorIndex-E_FIQEXPL_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h136 #define REG_FIQEXP_MASK_L 0x0026 macro
161 #define REG_FIQEXP_MASK_L 0x0026 macro
/utopia/UTPA2-700.0.x/mxlib/hal/mustang/
H A DhalCHIP.c428 IRQ_REG(REG_FIQEXP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
457 IRQ_REG(REG_FIQEXP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQEXPL_START)); in CHIP_EnableIRQ()
486 IRQ_REG(REG_FIQEXP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
517 IRQ_REG(REG_FIQEXP_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQEXPL_START)); in CHIP_DisableIRQ()
/utopia/UTPA2-700.0.x/mxlib/hal/messi/
H A DhalCHIP.c428 IRQ_REG(REG_FIQEXP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
457 IRQ_REG(REG_FIQEXP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQEXPL_START)); in CHIP_EnableIRQ()
486 IRQ_REG(REG_FIQEXP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
517 IRQ_REG(REG_FIQEXP_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQEXPL_START)); in CHIP_DisableIRQ()
/utopia/UTPA2-700.0.x/mxlib/hal/M7621/
H A DhalCHIP.c445 IRQ_REG(REG_FIQEXP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
474 IRQ_REG(REG_FIQEXP_MASK_L) &= ~(0x1 << (u8VectorIndex-E_FIQEXPL_START) ); in CHIP_EnableIRQ()
504 IRQ_REG(REG_FIQEXP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
535 IRQ_REG(REG_FIQEXP_MASK_L) |= (0x1 << (u8VectorIndex-E_FIQEXPL_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h136 #define REG_FIQEXP_MASK_L 0x0026 macro
162 #define REG_FIQEXP_MASK_L 0x0026 macro

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