Home
last modified time | relevance | path

Searched refs:REG_FIQEXP_MASK_H (Results 1 – 25 of 28) sorted by relevance

12

/utopia/UTPA2-700.0.x/mxlib/hal/k7u/
H A DhalCHIP.c514 IRQ_REG(REG_FIQEXP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
559 IRQ_REG(REG_FIQEXP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQEXPH_START)); in CHIP_EnableIRQ()
593 IRQ_REG(REG_FIQEXP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
641 IRQ_REG(REG_FIQEXP_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQEXPH_START)); in CHIP_DisableIRQ()
1650 IRQ_REG(REG_FIQEXP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
1695 IRQ_REG(REG_FIQEXP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQEXPH_START)); in CHIP_EnableIRQ()
1729 IRQ_REG(REG_FIQEXP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
1777 IRQ_REG(REG_FIQEXP_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQEXPH_START)); in CHIP_DisableIRQ()
H A DregCHIP.h118 #define REG_FIQEXP_MASK_H 0x0027 macro
145 #define REG_FIQEXP_MASK_H (REG_INT_BASE_ADDR + 0x0007) macro
/utopia/UTPA2-700.0.x/mxlib/hal/k6lite/
H A DhalCHIP.c514 IRQ_REG(REG_FIQEXP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
559 IRQ_REG(REG_FIQEXP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQEXPH_START)); in CHIP_EnableIRQ()
593 IRQ_REG(REG_FIQEXP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
641 IRQ_REG(REG_FIQEXP_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQEXPH_START)); in CHIP_DisableIRQ()
1650 IRQ_REG(REG_FIQEXP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
1695 IRQ_REG(REG_FIQEXP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQEXPH_START)); in CHIP_EnableIRQ()
1729 IRQ_REG(REG_FIQEXP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
1777 IRQ_REG(REG_FIQEXP_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQEXPH_START)); in CHIP_DisableIRQ()
H A DregCHIP.h118 #define REG_FIQEXP_MASK_H 0x0027 macro
145 #define REG_FIQEXP_MASK_H (REG_INT_BASE_ADDR + 0x0007) macro
/utopia/UTPA2-700.0.x/mxlib/hal/curry/
H A DhalCHIP.c514 IRQ_REG(REG_FIQEXP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
559 IRQ_REG(REG_FIQEXP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQEXPH_START)); in CHIP_EnableIRQ()
593 IRQ_REG(REG_FIQEXP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
641 IRQ_REG(REG_FIQEXP_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQEXPH_START)); in CHIP_DisableIRQ()
1637 IRQ_REG(REG_FIQEXP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
1682 IRQ_REG(REG_FIQEXP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQEXPH_START)); in CHIP_EnableIRQ()
1716 IRQ_REG(REG_FIQEXP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
1764 IRQ_REG(REG_FIQEXP_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQEXPH_START)); in CHIP_DisableIRQ()
H A DregCHIP.h118 #define REG_FIQEXP_MASK_H 0x0027 macro
145 #define REG_FIQEXP_MASK_H (REG_INT_BASE_ADDR + 0x0007) macro
/utopia/UTPA2-700.0.x/mxlib/hal/kano/
H A DhalCHIP.c514 IRQ_REG(REG_FIQEXP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
559 IRQ_REG(REG_FIQEXP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQEXPH_START)); in CHIP_EnableIRQ()
593 IRQ_REG(REG_FIQEXP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
641 IRQ_REG(REG_FIQEXP_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQEXPH_START)); in CHIP_DisableIRQ()
1650 IRQ_REG(REG_FIQEXP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
1695 IRQ_REG(REG_FIQEXP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQEXPH_START)); in CHIP_EnableIRQ()
1729 IRQ_REG(REG_FIQEXP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
1777 IRQ_REG(REG_FIQEXP_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQEXPH_START)); in CHIP_DisableIRQ()
H A DregCHIP.h118 #define REG_FIQEXP_MASK_H 0x0027 macro
145 #define REG_FIQEXP_MASK_H (REG_INT_BASE_ADDR + 0x0007) macro
/utopia/UTPA2-700.0.x/mxlib/hal/k6/
H A DhalCHIP.c514 IRQ_REG(REG_FIQEXP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
559 IRQ_REG(REG_FIQEXP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQEXPH_START)); in CHIP_EnableIRQ()
593 IRQ_REG(REG_FIQEXP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
641 IRQ_REG(REG_FIQEXP_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQEXPH_START)); in CHIP_DisableIRQ()
1650 IRQ_REG(REG_FIQEXP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
1695 IRQ_REG(REG_FIQEXP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQEXPH_START)); in CHIP_EnableIRQ()
1729 IRQ_REG(REG_FIQEXP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
1777 IRQ_REG(REG_FIQEXP_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQEXPH_START)); in CHIP_DisableIRQ()
H A DregCHIP.h118 #define REG_FIQEXP_MASK_H 0x0027 macro
145 #define REG_FIQEXP_MASK_H (REG_INT_BASE_ADDR + 0x0007) macro
/utopia/UTPA2-700.0.x/mxlib/hal/M7821/
H A DhalCHIP.c446 IRQ_REG(REG_FIQEXP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
478 IRQ_REG(REG_FIQEXP_MASK_H) &= ~(0x1 << (u8VectorIndex-E_FIQEXPH_START) ); in CHIP_EnableIRQ()
505 IRQ_REG(REG_FIQEXP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
540 IRQ_REG(REG_FIQEXP_MASK_H) |= (0x1 << (u8VectorIndex-E_FIQEXPH_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h137 #define REG_FIQEXP_MASK_H 0x0027 macro
163 #define REG_FIQEXP_MASK_H 0x0027 macro
/utopia/UTPA2-700.0.x/mxlib/hal/maxim/
H A DhalCHIP.c446 IRQ_REG(REG_FIQEXP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
478 IRQ_REG(REG_FIQEXP_MASK_H) &= ~(0x1 << (u8VectorIndex-E_FIQEXPH_START) ); in CHIP_EnableIRQ()
505 IRQ_REG(REG_FIQEXP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
540 IRQ_REG(REG_FIQEXP_MASK_H) |= (0x1 << (u8VectorIndex-E_FIQEXPH_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h137 #define REG_FIQEXP_MASK_H 0x0027 macro
162 #define REG_FIQEXP_MASK_H 0x0027 macro
/utopia/UTPA2-700.0.x/mxlib/hal/marcus/
H A DhalCHIP.c446 IRQ_REG(REG_FIQEXP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
478 IRQ_REG(REG_FIQEXP_MASK_H) &= ~(0x1 << (u8VectorIndex-E_FIQEXPH_START) ); in CHIP_EnableIRQ()
505 IRQ_REG(REG_FIQEXP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
540 IRQ_REG(REG_FIQEXP_MASK_H) |= (0x1 << (u8VectorIndex-E_FIQEXPH_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h137 #define REG_FIQEXP_MASK_H 0x0027 macro
162 #define REG_FIQEXP_MASK_H 0x0027 macro
/utopia/UTPA2-700.0.x/mxlib/hal/mainz/
H A DhalCHIP.c429 IRQ_REG(REG_FIQEXP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
461 IRQ_REG(REG_FIQEXP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQEXPH_START)); in CHIP_EnableIRQ()
487 IRQ_REG(REG_FIQEXP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
522 IRQ_REG(REG_FIQEXP_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQEXPH_START)); in CHIP_DisableIRQ()
/utopia/UTPA2-700.0.x/mxlib/hal/maserati/
H A DhalCHIP.c446 IRQ_REG(REG_FIQEXP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
478 IRQ_REG(REG_FIQEXP_MASK_H) &= ~(0x1 << (u8VectorIndex-E_FIQEXPH_START) ); in CHIP_EnableIRQ()
505 IRQ_REG(REG_FIQEXP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
540 IRQ_REG(REG_FIQEXP_MASK_H) |= (0x1 << (u8VectorIndex-E_FIQEXPH_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h137 #define REG_FIQEXP_MASK_H 0x0027 macro
162 #define REG_FIQEXP_MASK_H 0x0027 macro
/utopia/UTPA2-700.0.x/mxlib/hal/manhattan/
H A DhalCHIP.c446 IRQ_REG(REG_FIQEXP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
478 IRQ_REG(REG_FIQEXP_MASK_H) &= ~(0x1 << (u8VectorIndex-E_FIQEXPH_START) ); in CHIP_EnableIRQ()
505 IRQ_REG(REG_FIQEXP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
540 IRQ_REG(REG_FIQEXP_MASK_H) |= (0x1 << (u8VectorIndex-E_FIQEXPH_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h137 #define REG_FIQEXP_MASK_H 0x0027 macro
162 #define REG_FIQEXP_MASK_H 0x0027 macro
/utopia/UTPA2-700.0.x/mxlib/hal/mustang/
H A DhalCHIP.c429 IRQ_REG(REG_FIQEXP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
461 IRQ_REG(REG_FIQEXP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQEXPH_START)); in CHIP_EnableIRQ()
487 IRQ_REG(REG_FIQEXP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
522 IRQ_REG(REG_FIQEXP_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQEXPH_START)); in CHIP_DisableIRQ()
/utopia/UTPA2-700.0.x/mxlib/hal/messi/
H A DhalCHIP.c429 IRQ_REG(REG_FIQEXP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
461 IRQ_REG(REG_FIQEXP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQEXPH_START)); in CHIP_EnableIRQ()
487 IRQ_REG(REG_FIQEXP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
522 IRQ_REG(REG_FIQEXP_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQEXPH_START)); in CHIP_DisableIRQ()
/utopia/UTPA2-700.0.x/mxlib/hal/M7621/
H A DhalCHIP.c446 IRQ_REG(REG_FIQEXP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
478 IRQ_REG(REG_FIQEXP_MASK_H) &= ~(0x1 << (u8VectorIndex-E_FIQEXPH_START) ); in CHIP_EnableIRQ()
505 IRQ_REG(REG_FIQEXP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
540 IRQ_REG(REG_FIQEXP_MASK_H) |= (0x1 << (u8VectorIndex-E_FIQEXPH_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h137 #define REG_FIQEXP_MASK_H 0x0027 macro
163 #define REG_FIQEXP_MASK_H 0x0027 macro

12