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Searched refs:REG_DVI_RSV_DUAL_P3_BASE (Results 1 – 25 of 27) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h5429 #define REG_DVI_RSV_DUAL_P3_00_L (REG_DVI_RSV_DUAL_P3_BASE + 0x00)
5430 #define REG_DVI_RSV_DUAL_P3_00_H (REG_DVI_RSV_DUAL_P3_BASE + 0x01)
5431 #define REG_DVI_RSV_DUAL_P3_01_L (REG_DVI_RSV_DUAL_P3_BASE + 0x02)
5432 #define REG_DVI_RSV_DUAL_P3_01_H (REG_DVI_RSV_DUAL_P3_BASE + 0x03)
5433 #define REG_DVI_RSV_DUAL_P3_02_L (REG_DVI_RSV_DUAL_P3_BASE + 0x04)
5434 #define REG_DVI_RSV_DUAL_P3_02_H (REG_DVI_RSV_DUAL_P3_BASE + 0x05)
5435 #define REG_DVI_RSV_DUAL_P3_03_L (REG_DVI_RSV_DUAL_P3_BASE + 0x06)
5436 #define REG_DVI_RSV_DUAL_P3_03_H (REG_DVI_RSV_DUAL_P3_BASE + 0x07)
5437 #define REG_DVI_RSV_DUAL_P3_04_L (REG_DVI_RSV_DUAL_P3_BASE + 0x08)
5438 #define REG_DVI_RSV_DUAL_P3_04_H (REG_DVI_RSV_DUAL_P3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h598 #define REG_DVI_RSV_DUAL_P3_BASE 0x171A00UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h5431 #define REG_DVI_RSV_DUAL_P3_00_L (REG_DVI_RSV_DUAL_P3_BASE + 0x00)
5432 #define REG_DVI_RSV_DUAL_P3_00_H (REG_DVI_RSV_DUAL_P3_BASE + 0x01)
5433 #define REG_DVI_RSV_DUAL_P3_01_L (REG_DVI_RSV_DUAL_P3_BASE + 0x02)
5434 #define REG_DVI_RSV_DUAL_P3_01_H (REG_DVI_RSV_DUAL_P3_BASE + 0x03)
5435 #define REG_DVI_RSV_DUAL_P3_02_L (REG_DVI_RSV_DUAL_P3_BASE + 0x04)
5436 #define REG_DVI_RSV_DUAL_P3_02_H (REG_DVI_RSV_DUAL_P3_BASE + 0x05)
5437 #define REG_DVI_RSV_DUAL_P3_03_L (REG_DVI_RSV_DUAL_P3_BASE + 0x06)
5438 #define REG_DVI_RSV_DUAL_P3_03_H (REG_DVI_RSV_DUAL_P3_BASE + 0x07)
5439 #define REG_DVI_RSV_DUAL_P3_04_L (REG_DVI_RSV_DUAL_P3_BASE + 0x08)
5440 #define REG_DVI_RSV_DUAL_P3_04_H (REG_DVI_RSV_DUAL_P3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h580 #define REG_DVI_RSV_DUAL_P3_BASE REG_DVI_RSV_DUAL_P0_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h5423 #define REG_DVI_RSV_DUAL_P3_00_L (REG_DVI_RSV_DUAL_P3_BASE + 0x00)
5424 #define REG_DVI_RSV_DUAL_P3_00_H (REG_DVI_RSV_DUAL_P3_BASE + 0x01)
5425 #define REG_DVI_RSV_DUAL_P3_01_L (REG_DVI_RSV_DUAL_P3_BASE + 0x02)
5426 #define REG_DVI_RSV_DUAL_P3_01_H (REG_DVI_RSV_DUAL_P3_BASE + 0x03)
5427 #define REG_DVI_RSV_DUAL_P3_02_L (REG_DVI_RSV_DUAL_P3_BASE + 0x04)
5428 #define REG_DVI_RSV_DUAL_P3_02_H (REG_DVI_RSV_DUAL_P3_BASE + 0x05)
5429 #define REG_DVI_RSV_DUAL_P3_03_L (REG_DVI_RSV_DUAL_P3_BASE + 0x06)
5430 #define REG_DVI_RSV_DUAL_P3_03_H (REG_DVI_RSV_DUAL_P3_BASE + 0x07)
5431 #define REG_DVI_RSV_DUAL_P3_04_L (REG_DVI_RSV_DUAL_P3_BASE + 0x08)
5432 #define REG_DVI_RSV_DUAL_P3_04_H (REG_DVI_RSV_DUAL_P3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h558 #define REG_DVI_RSV_DUAL_P3_BASE 0x171A00UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h5431 #define REG_DVI_RSV_DUAL_P3_00_L (REG_DVI_RSV_DUAL_P3_BASE + 0x00)
5432 #define REG_DVI_RSV_DUAL_P3_00_H (REG_DVI_RSV_DUAL_P3_BASE + 0x01)
5433 #define REG_DVI_RSV_DUAL_P3_01_L (REG_DVI_RSV_DUAL_P3_BASE + 0x02)
5434 #define REG_DVI_RSV_DUAL_P3_01_H (REG_DVI_RSV_DUAL_P3_BASE + 0x03)
5435 #define REG_DVI_RSV_DUAL_P3_02_L (REG_DVI_RSV_DUAL_P3_BASE + 0x04)
5436 #define REG_DVI_RSV_DUAL_P3_02_H (REG_DVI_RSV_DUAL_P3_BASE + 0x05)
5437 #define REG_DVI_RSV_DUAL_P3_03_L (REG_DVI_RSV_DUAL_P3_BASE + 0x06)
5438 #define REG_DVI_RSV_DUAL_P3_03_H (REG_DVI_RSV_DUAL_P3_BASE + 0x07)
5439 #define REG_DVI_RSV_DUAL_P3_04_L (REG_DVI_RSV_DUAL_P3_BASE + 0x08)
5440 #define REG_DVI_RSV_DUAL_P3_04_H (REG_DVI_RSV_DUAL_P3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h582 #define REG_DVI_RSV_DUAL_P3_BASE REG_DVI_RSV_DUAL_P0_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h5423 #define REG_DVI_RSV_DUAL_P3_00_L (REG_DVI_RSV_DUAL_P3_BASE + 0x00)
5424 #define REG_DVI_RSV_DUAL_P3_00_H (REG_DVI_RSV_DUAL_P3_BASE + 0x01)
5425 #define REG_DVI_RSV_DUAL_P3_01_L (REG_DVI_RSV_DUAL_P3_BASE + 0x02)
5426 #define REG_DVI_RSV_DUAL_P3_01_H (REG_DVI_RSV_DUAL_P3_BASE + 0x03)
5427 #define REG_DVI_RSV_DUAL_P3_02_L (REG_DVI_RSV_DUAL_P3_BASE + 0x04)
5428 #define REG_DVI_RSV_DUAL_P3_02_H (REG_DVI_RSV_DUAL_P3_BASE + 0x05)
5429 #define REG_DVI_RSV_DUAL_P3_03_L (REG_DVI_RSV_DUAL_P3_BASE + 0x06)
5430 #define REG_DVI_RSV_DUAL_P3_03_H (REG_DVI_RSV_DUAL_P3_BASE + 0x07)
5431 #define REG_DVI_RSV_DUAL_P3_04_L (REG_DVI_RSV_DUAL_P3_BASE + 0x08)
5432 #define REG_DVI_RSV_DUAL_P3_04_H (REG_DVI_RSV_DUAL_P3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h585 #define REG_DVI_RSV_DUAL_P3_BASE 0x171A00UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h5431 #define REG_DVI_RSV_DUAL_P3_00_L (REG_DVI_RSV_DUAL_P3_BASE + 0x00)
5432 #define REG_DVI_RSV_DUAL_P3_00_H (REG_DVI_RSV_DUAL_P3_BASE + 0x01)
5433 #define REG_DVI_RSV_DUAL_P3_01_L (REG_DVI_RSV_DUAL_P3_BASE + 0x02)
5434 #define REG_DVI_RSV_DUAL_P3_01_H (REG_DVI_RSV_DUAL_P3_BASE + 0x03)
5435 #define REG_DVI_RSV_DUAL_P3_02_L (REG_DVI_RSV_DUAL_P3_BASE + 0x04)
5436 #define REG_DVI_RSV_DUAL_P3_02_H (REG_DVI_RSV_DUAL_P3_BASE + 0x05)
5437 #define REG_DVI_RSV_DUAL_P3_03_L (REG_DVI_RSV_DUAL_P3_BASE + 0x06)
5438 #define REG_DVI_RSV_DUAL_P3_03_H (REG_DVI_RSV_DUAL_P3_BASE + 0x07)
5439 #define REG_DVI_RSV_DUAL_P3_04_L (REG_DVI_RSV_DUAL_P3_BASE + 0x08)
5440 #define REG_DVI_RSV_DUAL_P3_04_H (REG_DVI_RSV_DUAL_P3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h574 #define REG_DVI_RSV_DUAL_P3_BASE REG_DVI_RSV_DUAL_P0_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h5431 #define REG_DVI_RSV_DUAL_P3_00_L (REG_DVI_RSV_DUAL_P3_BASE + 0x00)
5432 #define REG_DVI_RSV_DUAL_P3_00_H (REG_DVI_RSV_DUAL_P3_BASE + 0x01)
5433 #define REG_DVI_RSV_DUAL_P3_01_L (REG_DVI_RSV_DUAL_P3_BASE + 0x02)
5434 #define REG_DVI_RSV_DUAL_P3_01_H (REG_DVI_RSV_DUAL_P3_BASE + 0x03)
5435 #define REG_DVI_RSV_DUAL_P3_02_L (REG_DVI_RSV_DUAL_P3_BASE + 0x04)
5436 #define REG_DVI_RSV_DUAL_P3_02_H (REG_DVI_RSV_DUAL_P3_BASE + 0x05)
5437 #define REG_DVI_RSV_DUAL_P3_03_L (REG_DVI_RSV_DUAL_P3_BASE + 0x06)
5438 #define REG_DVI_RSV_DUAL_P3_03_H (REG_DVI_RSV_DUAL_P3_BASE + 0x07)
5439 #define REG_DVI_RSV_DUAL_P3_04_L (REG_DVI_RSV_DUAL_P3_BASE + 0x08)
5440 #define REG_DVI_RSV_DUAL_P3_04_H (REG_DVI_RSV_DUAL_P3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h580 #define REG_DVI_RSV_DUAL_P3_BASE REG_DVI_RSV_DUAL_P0_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h5423 #define REG_DVI_RSV_DUAL_P3_00_L (REG_DVI_RSV_DUAL_P3_BASE + 0x00)
5424 #define REG_DVI_RSV_DUAL_P3_00_H (REG_DVI_RSV_DUAL_P3_BASE + 0x01)
5425 #define REG_DVI_RSV_DUAL_P3_01_L (REG_DVI_RSV_DUAL_P3_BASE + 0x02)
5426 #define REG_DVI_RSV_DUAL_P3_01_H (REG_DVI_RSV_DUAL_P3_BASE + 0x03)
5427 #define REG_DVI_RSV_DUAL_P3_02_L (REG_DVI_RSV_DUAL_P3_BASE + 0x04)
5428 #define REG_DVI_RSV_DUAL_P3_02_H (REG_DVI_RSV_DUAL_P3_BASE + 0x05)
5429 #define REG_DVI_RSV_DUAL_P3_03_L (REG_DVI_RSV_DUAL_P3_BASE + 0x06)
5430 #define REG_DVI_RSV_DUAL_P3_03_H (REG_DVI_RSV_DUAL_P3_BASE + 0x07)
5431 #define REG_DVI_RSV_DUAL_P3_04_L (REG_DVI_RSV_DUAL_P3_BASE + 0x08)
5432 #define REG_DVI_RSV_DUAL_P3_04_H (REG_DVI_RSV_DUAL_P3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h556 #define REG_DVI_RSV_DUAL_P3_BASE 0x171A00UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h5424 #define REG_DVI_RSV_DUAL_P3_00_L (REG_DVI_RSV_DUAL_P3_BASE + 0x00)
5425 #define REG_DVI_RSV_DUAL_P3_00_H (REG_DVI_RSV_DUAL_P3_BASE + 0x01)
5426 #define REG_DVI_RSV_DUAL_P3_01_L (REG_DVI_RSV_DUAL_P3_BASE + 0x02)
5427 #define REG_DVI_RSV_DUAL_P3_01_H (REG_DVI_RSV_DUAL_P3_BASE + 0x03)
5428 #define REG_DVI_RSV_DUAL_P3_02_L (REG_DVI_RSV_DUAL_P3_BASE + 0x04)
5429 #define REG_DVI_RSV_DUAL_P3_02_H (REG_DVI_RSV_DUAL_P3_BASE + 0x05)
5430 #define REG_DVI_RSV_DUAL_P3_03_L (REG_DVI_RSV_DUAL_P3_BASE + 0x06)
5431 #define REG_DVI_RSV_DUAL_P3_03_H (REG_DVI_RSV_DUAL_P3_BASE + 0x07)
5432 #define REG_DVI_RSV_DUAL_P3_04_L (REG_DVI_RSV_DUAL_P3_BASE + 0x08)
5433 #define REG_DVI_RSV_DUAL_P3_04_H (REG_DVI_RSV_DUAL_P3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h539 #define REG_DVI_RSV_DUAL_P3_BASE 0x171A00UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h5423 #define REG_DVI_RSV_DUAL_P3_00_L (REG_DVI_RSV_DUAL_P3_BASE + 0x00)
5424 #define REG_DVI_RSV_DUAL_P3_00_H (REG_DVI_RSV_DUAL_P3_BASE + 0x01)
5425 #define REG_DVI_RSV_DUAL_P3_01_L (REG_DVI_RSV_DUAL_P3_BASE + 0x02)
5426 #define REG_DVI_RSV_DUAL_P3_01_H (REG_DVI_RSV_DUAL_P3_BASE + 0x03)
5427 #define REG_DVI_RSV_DUAL_P3_02_L (REG_DVI_RSV_DUAL_P3_BASE + 0x04)
5428 #define REG_DVI_RSV_DUAL_P3_02_H (REG_DVI_RSV_DUAL_P3_BASE + 0x05)
5429 #define REG_DVI_RSV_DUAL_P3_03_L (REG_DVI_RSV_DUAL_P3_BASE + 0x06)
5430 #define REG_DVI_RSV_DUAL_P3_03_H (REG_DVI_RSV_DUAL_P3_BASE + 0x07)
5431 #define REG_DVI_RSV_DUAL_P3_04_L (REG_DVI_RSV_DUAL_P3_BASE + 0x08)
5432 #define REG_DVI_RSV_DUAL_P3_04_H (REG_DVI_RSV_DUAL_P3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h632 #define REG_DVI_RSV_DUAL_P3_BASE 0x171A00UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h5429 #define REG_DVI_RSV_DUAL_P3_00_L (REG_DVI_RSV_DUAL_P3_BASE + 0x00)
5430 #define REG_DVI_RSV_DUAL_P3_00_H (REG_DVI_RSV_DUAL_P3_BASE + 0x01)
5431 #define REG_DVI_RSV_DUAL_P3_01_L (REG_DVI_RSV_DUAL_P3_BASE + 0x02)
5432 #define REG_DVI_RSV_DUAL_P3_01_H (REG_DVI_RSV_DUAL_P3_BASE + 0x03)
5433 #define REG_DVI_RSV_DUAL_P3_02_L (REG_DVI_RSV_DUAL_P3_BASE + 0x04)
5434 #define REG_DVI_RSV_DUAL_P3_02_H (REG_DVI_RSV_DUAL_P3_BASE + 0x05)
5435 #define REG_DVI_RSV_DUAL_P3_03_L (REG_DVI_RSV_DUAL_P3_BASE + 0x06)
5436 #define REG_DVI_RSV_DUAL_P3_03_H (REG_DVI_RSV_DUAL_P3_BASE + 0x07)
5437 #define REG_DVI_RSV_DUAL_P3_04_L (REG_DVI_RSV_DUAL_P3_BASE + 0x08)
5438 #define REG_DVI_RSV_DUAL_P3_04_H (REG_DVI_RSV_DUAL_P3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h644 #define REG_DVI_RSV_DUAL_P3_BASE 0x171A00UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h5429 #define REG_DVI_RSV_DUAL_P3_00_L (REG_DVI_RSV_DUAL_P3_BASE + 0x00)
5430 #define REG_DVI_RSV_DUAL_P3_00_H (REG_DVI_RSV_DUAL_P3_BASE + 0x01)
5431 #define REG_DVI_RSV_DUAL_P3_01_L (REG_DVI_RSV_DUAL_P3_BASE + 0x02)
5432 #define REG_DVI_RSV_DUAL_P3_01_H (REG_DVI_RSV_DUAL_P3_BASE + 0x03)
5433 #define REG_DVI_RSV_DUAL_P3_02_L (REG_DVI_RSV_DUAL_P3_BASE + 0x04)
5434 #define REG_DVI_RSV_DUAL_P3_02_H (REG_DVI_RSV_DUAL_P3_BASE + 0x05)
5435 #define REG_DVI_RSV_DUAL_P3_03_L (REG_DVI_RSV_DUAL_P3_BASE + 0x06)
5436 #define REG_DVI_RSV_DUAL_P3_03_H (REG_DVI_RSV_DUAL_P3_BASE + 0x07)
5437 #define REG_DVI_RSV_DUAL_P3_04_L (REG_DVI_RSV_DUAL_P3_BASE + 0x08)
5438 #define REG_DVI_RSV_DUAL_P3_04_H (REG_DVI_RSV_DUAL_P3_BASE + 0x09)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_hdmi.h5429 #define REG_DVI_RSV_DUAL_P3_00_L (REG_DVI_RSV_DUAL_P3_BASE + 0x00)
5430 #define REG_DVI_RSV_DUAL_P3_00_H (REG_DVI_RSV_DUAL_P3_BASE + 0x01)
5431 #define REG_DVI_RSV_DUAL_P3_01_L (REG_DVI_RSV_DUAL_P3_BASE + 0x02)
5432 #define REG_DVI_RSV_DUAL_P3_01_H (REG_DVI_RSV_DUAL_P3_BASE + 0x03)
5433 #define REG_DVI_RSV_DUAL_P3_02_L (REG_DVI_RSV_DUAL_P3_BASE + 0x04)
5434 #define REG_DVI_RSV_DUAL_P3_02_H (REG_DVI_RSV_DUAL_P3_BASE + 0x05)
5435 #define REG_DVI_RSV_DUAL_P3_03_L (REG_DVI_RSV_DUAL_P3_BASE + 0x06)
5436 #define REG_DVI_RSV_DUAL_P3_03_H (REG_DVI_RSV_DUAL_P3_BASE + 0x07)
5437 #define REG_DVI_RSV_DUAL_P3_04_L (REG_DVI_RSV_DUAL_P3_BASE + 0x08)
5438 #define REG_DVI_RSV_DUAL_P3_04_H (REG_DVI_RSV_DUAL_P3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h649 #define REG_DVI_RSV_DUAL_P3_BASE 0x171A00UL macro

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