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Searched refs:REG_DVI_RSV_DUAL_P2_BASE (Results 1 – 25 of 27) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h4893 #define REG_DVI_RSV_DUAL_P2_00_L (REG_DVI_RSV_DUAL_P2_BASE + 0x00)
4894 #define REG_DVI_RSV_DUAL_P2_00_H (REG_DVI_RSV_DUAL_P2_BASE + 0x01)
4895 #define REG_DVI_RSV_DUAL_P2_01_L (REG_DVI_RSV_DUAL_P2_BASE + 0x02)
4896 #define REG_DVI_RSV_DUAL_P2_01_H (REG_DVI_RSV_DUAL_P2_BASE + 0x03)
4897 #define REG_DVI_RSV_DUAL_P2_02_L (REG_DVI_RSV_DUAL_P2_BASE + 0x04)
4898 #define REG_DVI_RSV_DUAL_P2_02_H (REG_DVI_RSV_DUAL_P2_BASE + 0x05)
4899 #define REG_DVI_RSV_DUAL_P2_03_L (REG_DVI_RSV_DUAL_P2_BASE + 0x06)
4900 #define REG_DVI_RSV_DUAL_P2_03_H (REG_DVI_RSV_DUAL_P2_BASE + 0x07)
4901 #define REG_DVI_RSV_DUAL_P2_04_L (REG_DVI_RSV_DUAL_P2_BASE + 0x08)
4902 #define REG_DVI_RSV_DUAL_P2_04_H (REG_DVI_RSV_DUAL_P2_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h595 #define REG_DVI_RSV_DUAL_P2_BASE 0x171700UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h4895 #define REG_DVI_RSV_DUAL_P2_00_L (REG_DVI_RSV_DUAL_P2_BASE + 0x00)
4896 #define REG_DVI_RSV_DUAL_P2_00_H (REG_DVI_RSV_DUAL_P2_BASE + 0x01)
4897 #define REG_DVI_RSV_DUAL_P2_01_L (REG_DVI_RSV_DUAL_P2_BASE + 0x02)
4898 #define REG_DVI_RSV_DUAL_P2_01_H (REG_DVI_RSV_DUAL_P2_BASE + 0x03)
4899 #define REG_DVI_RSV_DUAL_P2_02_L (REG_DVI_RSV_DUAL_P2_BASE + 0x04)
4900 #define REG_DVI_RSV_DUAL_P2_02_H (REG_DVI_RSV_DUAL_P2_BASE + 0x05)
4901 #define REG_DVI_RSV_DUAL_P2_03_L (REG_DVI_RSV_DUAL_P2_BASE + 0x06)
4902 #define REG_DVI_RSV_DUAL_P2_03_H (REG_DVI_RSV_DUAL_P2_BASE + 0x07)
4903 #define REG_DVI_RSV_DUAL_P2_04_L (REG_DVI_RSV_DUAL_P2_BASE + 0x08)
4904 #define REG_DVI_RSV_DUAL_P2_04_H (REG_DVI_RSV_DUAL_P2_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h577 #define REG_DVI_RSV_DUAL_P2_BASE REG_DVI_RSV_DUAL_P0_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h4889 #define REG_DVI_RSV_DUAL_P2_00_L (REG_DVI_RSV_DUAL_P2_BASE + 0x00)
4890 #define REG_DVI_RSV_DUAL_P2_00_H (REG_DVI_RSV_DUAL_P2_BASE + 0x01)
4891 #define REG_DVI_RSV_DUAL_P2_01_L (REG_DVI_RSV_DUAL_P2_BASE + 0x02)
4892 #define REG_DVI_RSV_DUAL_P2_01_H (REG_DVI_RSV_DUAL_P2_BASE + 0x03)
4893 #define REG_DVI_RSV_DUAL_P2_02_L (REG_DVI_RSV_DUAL_P2_BASE + 0x04)
4894 #define REG_DVI_RSV_DUAL_P2_02_H (REG_DVI_RSV_DUAL_P2_BASE + 0x05)
4895 #define REG_DVI_RSV_DUAL_P2_03_L (REG_DVI_RSV_DUAL_P2_BASE + 0x06)
4896 #define REG_DVI_RSV_DUAL_P2_03_H (REG_DVI_RSV_DUAL_P2_BASE + 0x07)
4897 #define REG_DVI_RSV_DUAL_P2_04_L (REG_DVI_RSV_DUAL_P2_BASE + 0x08)
4898 #define REG_DVI_RSV_DUAL_P2_04_H (REG_DVI_RSV_DUAL_P2_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h555 #define REG_DVI_RSV_DUAL_P2_BASE 0x171700UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h4895 #define REG_DVI_RSV_DUAL_P2_00_L (REG_DVI_RSV_DUAL_P2_BASE + 0x00)
4896 #define REG_DVI_RSV_DUAL_P2_00_H (REG_DVI_RSV_DUAL_P2_BASE + 0x01)
4897 #define REG_DVI_RSV_DUAL_P2_01_L (REG_DVI_RSV_DUAL_P2_BASE + 0x02)
4898 #define REG_DVI_RSV_DUAL_P2_01_H (REG_DVI_RSV_DUAL_P2_BASE + 0x03)
4899 #define REG_DVI_RSV_DUAL_P2_02_L (REG_DVI_RSV_DUAL_P2_BASE + 0x04)
4900 #define REG_DVI_RSV_DUAL_P2_02_H (REG_DVI_RSV_DUAL_P2_BASE + 0x05)
4901 #define REG_DVI_RSV_DUAL_P2_03_L (REG_DVI_RSV_DUAL_P2_BASE + 0x06)
4902 #define REG_DVI_RSV_DUAL_P2_03_H (REG_DVI_RSV_DUAL_P2_BASE + 0x07)
4903 #define REG_DVI_RSV_DUAL_P2_04_L (REG_DVI_RSV_DUAL_P2_BASE + 0x08)
4904 #define REG_DVI_RSV_DUAL_P2_04_H (REG_DVI_RSV_DUAL_P2_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h579 #define REG_DVI_RSV_DUAL_P2_BASE REG_DVI_RSV_DUAL_P0_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h4889 #define REG_DVI_RSV_DUAL_P2_00_L (REG_DVI_RSV_DUAL_P2_BASE + 0x00)
4890 #define REG_DVI_RSV_DUAL_P2_00_H (REG_DVI_RSV_DUAL_P2_BASE + 0x01)
4891 #define REG_DVI_RSV_DUAL_P2_01_L (REG_DVI_RSV_DUAL_P2_BASE + 0x02)
4892 #define REG_DVI_RSV_DUAL_P2_01_H (REG_DVI_RSV_DUAL_P2_BASE + 0x03)
4893 #define REG_DVI_RSV_DUAL_P2_02_L (REG_DVI_RSV_DUAL_P2_BASE + 0x04)
4894 #define REG_DVI_RSV_DUAL_P2_02_H (REG_DVI_RSV_DUAL_P2_BASE + 0x05)
4895 #define REG_DVI_RSV_DUAL_P2_03_L (REG_DVI_RSV_DUAL_P2_BASE + 0x06)
4896 #define REG_DVI_RSV_DUAL_P2_03_H (REG_DVI_RSV_DUAL_P2_BASE + 0x07)
4897 #define REG_DVI_RSV_DUAL_P2_04_L (REG_DVI_RSV_DUAL_P2_BASE + 0x08)
4898 #define REG_DVI_RSV_DUAL_P2_04_H (REG_DVI_RSV_DUAL_P2_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h582 #define REG_DVI_RSV_DUAL_P2_BASE 0x171700UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h4895 #define REG_DVI_RSV_DUAL_P2_00_L (REG_DVI_RSV_DUAL_P2_BASE + 0x00)
4896 #define REG_DVI_RSV_DUAL_P2_00_H (REG_DVI_RSV_DUAL_P2_BASE + 0x01)
4897 #define REG_DVI_RSV_DUAL_P2_01_L (REG_DVI_RSV_DUAL_P2_BASE + 0x02)
4898 #define REG_DVI_RSV_DUAL_P2_01_H (REG_DVI_RSV_DUAL_P2_BASE + 0x03)
4899 #define REG_DVI_RSV_DUAL_P2_02_L (REG_DVI_RSV_DUAL_P2_BASE + 0x04)
4900 #define REG_DVI_RSV_DUAL_P2_02_H (REG_DVI_RSV_DUAL_P2_BASE + 0x05)
4901 #define REG_DVI_RSV_DUAL_P2_03_L (REG_DVI_RSV_DUAL_P2_BASE + 0x06)
4902 #define REG_DVI_RSV_DUAL_P2_03_H (REG_DVI_RSV_DUAL_P2_BASE + 0x07)
4903 #define REG_DVI_RSV_DUAL_P2_04_L (REG_DVI_RSV_DUAL_P2_BASE + 0x08)
4904 #define REG_DVI_RSV_DUAL_P2_04_H (REG_DVI_RSV_DUAL_P2_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h571 #define REG_DVI_RSV_DUAL_P2_BASE REG_DVI_RSV_DUAL_P0_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h4895 #define REG_DVI_RSV_DUAL_P2_00_L (REG_DVI_RSV_DUAL_P2_BASE + 0x00)
4896 #define REG_DVI_RSV_DUAL_P2_00_H (REG_DVI_RSV_DUAL_P2_BASE + 0x01)
4897 #define REG_DVI_RSV_DUAL_P2_01_L (REG_DVI_RSV_DUAL_P2_BASE + 0x02)
4898 #define REG_DVI_RSV_DUAL_P2_01_H (REG_DVI_RSV_DUAL_P2_BASE + 0x03)
4899 #define REG_DVI_RSV_DUAL_P2_02_L (REG_DVI_RSV_DUAL_P2_BASE + 0x04)
4900 #define REG_DVI_RSV_DUAL_P2_02_H (REG_DVI_RSV_DUAL_P2_BASE + 0x05)
4901 #define REG_DVI_RSV_DUAL_P2_03_L (REG_DVI_RSV_DUAL_P2_BASE + 0x06)
4902 #define REG_DVI_RSV_DUAL_P2_03_H (REG_DVI_RSV_DUAL_P2_BASE + 0x07)
4903 #define REG_DVI_RSV_DUAL_P2_04_L (REG_DVI_RSV_DUAL_P2_BASE + 0x08)
4904 #define REG_DVI_RSV_DUAL_P2_04_H (REG_DVI_RSV_DUAL_P2_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h577 #define REG_DVI_RSV_DUAL_P2_BASE REG_DVI_RSV_DUAL_P0_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h4889 #define REG_DVI_RSV_DUAL_P2_00_L (REG_DVI_RSV_DUAL_P2_BASE + 0x00)
4890 #define REG_DVI_RSV_DUAL_P2_00_H (REG_DVI_RSV_DUAL_P2_BASE + 0x01)
4891 #define REG_DVI_RSV_DUAL_P2_01_L (REG_DVI_RSV_DUAL_P2_BASE + 0x02)
4892 #define REG_DVI_RSV_DUAL_P2_01_H (REG_DVI_RSV_DUAL_P2_BASE + 0x03)
4893 #define REG_DVI_RSV_DUAL_P2_02_L (REG_DVI_RSV_DUAL_P2_BASE + 0x04)
4894 #define REG_DVI_RSV_DUAL_P2_02_H (REG_DVI_RSV_DUAL_P2_BASE + 0x05)
4895 #define REG_DVI_RSV_DUAL_P2_03_L (REG_DVI_RSV_DUAL_P2_BASE + 0x06)
4896 #define REG_DVI_RSV_DUAL_P2_03_H (REG_DVI_RSV_DUAL_P2_BASE + 0x07)
4897 #define REG_DVI_RSV_DUAL_P2_04_L (REG_DVI_RSV_DUAL_P2_BASE + 0x08)
4898 #define REG_DVI_RSV_DUAL_P2_04_H (REG_DVI_RSV_DUAL_P2_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h553 #define REG_DVI_RSV_DUAL_P2_BASE 0x171700UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h4890 #define REG_DVI_RSV_DUAL_P2_00_L (REG_DVI_RSV_DUAL_P2_BASE + 0x00)
4891 #define REG_DVI_RSV_DUAL_P2_00_H (REG_DVI_RSV_DUAL_P2_BASE + 0x01)
4892 #define REG_DVI_RSV_DUAL_P2_01_L (REG_DVI_RSV_DUAL_P2_BASE + 0x02)
4893 #define REG_DVI_RSV_DUAL_P2_01_H (REG_DVI_RSV_DUAL_P2_BASE + 0x03)
4894 #define REG_DVI_RSV_DUAL_P2_02_L (REG_DVI_RSV_DUAL_P2_BASE + 0x04)
4895 #define REG_DVI_RSV_DUAL_P2_02_H (REG_DVI_RSV_DUAL_P2_BASE + 0x05)
4896 #define REG_DVI_RSV_DUAL_P2_03_L (REG_DVI_RSV_DUAL_P2_BASE + 0x06)
4897 #define REG_DVI_RSV_DUAL_P2_03_H (REG_DVI_RSV_DUAL_P2_BASE + 0x07)
4898 #define REG_DVI_RSV_DUAL_P2_04_L (REG_DVI_RSV_DUAL_P2_BASE + 0x08)
4899 #define REG_DVI_RSV_DUAL_P2_04_H (REG_DVI_RSV_DUAL_P2_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h536 #define REG_DVI_RSV_DUAL_P2_BASE 0x171700UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h4889 #define REG_DVI_RSV_DUAL_P2_00_L (REG_DVI_RSV_DUAL_P2_BASE + 0x00)
4890 #define REG_DVI_RSV_DUAL_P2_00_H (REG_DVI_RSV_DUAL_P2_BASE + 0x01)
4891 #define REG_DVI_RSV_DUAL_P2_01_L (REG_DVI_RSV_DUAL_P2_BASE + 0x02)
4892 #define REG_DVI_RSV_DUAL_P2_01_H (REG_DVI_RSV_DUAL_P2_BASE + 0x03)
4893 #define REG_DVI_RSV_DUAL_P2_02_L (REG_DVI_RSV_DUAL_P2_BASE + 0x04)
4894 #define REG_DVI_RSV_DUAL_P2_02_H (REG_DVI_RSV_DUAL_P2_BASE + 0x05)
4895 #define REG_DVI_RSV_DUAL_P2_03_L (REG_DVI_RSV_DUAL_P2_BASE + 0x06)
4896 #define REG_DVI_RSV_DUAL_P2_03_H (REG_DVI_RSV_DUAL_P2_BASE + 0x07)
4897 #define REG_DVI_RSV_DUAL_P2_04_L (REG_DVI_RSV_DUAL_P2_BASE + 0x08)
4898 #define REG_DVI_RSV_DUAL_P2_04_H (REG_DVI_RSV_DUAL_P2_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h629 #define REG_DVI_RSV_DUAL_P2_BASE 0x171700UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h4893 #define REG_DVI_RSV_DUAL_P2_00_L (REG_DVI_RSV_DUAL_P2_BASE + 0x00)
4894 #define REG_DVI_RSV_DUAL_P2_00_H (REG_DVI_RSV_DUAL_P2_BASE + 0x01)
4895 #define REG_DVI_RSV_DUAL_P2_01_L (REG_DVI_RSV_DUAL_P2_BASE + 0x02)
4896 #define REG_DVI_RSV_DUAL_P2_01_H (REG_DVI_RSV_DUAL_P2_BASE + 0x03)
4897 #define REG_DVI_RSV_DUAL_P2_02_L (REG_DVI_RSV_DUAL_P2_BASE + 0x04)
4898 #define REG_DVI_RSV_DUAL_P2_02_H (REG_DVI_RSV_DUAL_P2_BASE + 0x05)
4899 #define REG_DVI_RSV_DUAL_P2_03_L (REG_DVI_RSV_DUAL_P2_BASE + 0x06)
4900 #define REG_DVI_RSV_DUAL_P2_03_H (REG_DVI_RSV_DUAL_P2_BASE + 0x07)
4901 #define REG_DVI_RSV_DUAL_P2_04_L (REG_DVI_RSV_DUAL_P2_BASE + 0x08)
4902 #define REG_DVI_RSV_DUAL_P2_04_H (REG_DVI_RSV_DUAL_P2_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h641 #define REG_DVI_RSV_DUAL_P2_BASE 0x171700UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h4893 #define REG_DVI_RSV_DUAL_P2_00_L (REG_DVI_RSV_DUAL_P2_BASE + 0x00)
4894 #define REG_DVI_RSV_DUAL_P2_00_H (REG_DVI_RSV_DUAL_P2_BASE + 0x01)
4895 #define REG_DVI_RSV_DUAL_P2_01_L (REG_DVI_RSV_DUAL_P2_BASE + 0x02)
4896 #define REG_DVI_RSV_DUAL_P2_01_H (REG_DVI_RSV_DUAL_P2_BASE + 0x03)
4897 #define REG_DVI_RSV_DUAL_P2_02_L (REG_DVI_RSV_DUAL_P2_BASE + 0x04)
4898 #define REG_DVI_RSV_DUAL_P2_02_H (REG_DVI_RSV_DUAL_P2_BASE + 0x05)
4899 #define REG_DVI_RSV_DUAL_P2_03_L (REG_DVI_RSV_DUAL_P2_BASE + 0x06)
4900 #define REG_DVI_RSV_DUAL_P2_03_H (REG_DVI_RSV_DUAL_P2_BASE + 0x07)
4901 #define REG_DVI_RSV_DUAL_P2_04_L (REG_DVI_RSV_DUAL_P2_BASE + 0x08)
4902 #define REG_DVI_RSV_DUAL_P2_04_H (REG_DVI_RSV_DUAL_P2_BASE + 0x09)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_hdmi.h4893 #define REG_DVI_RSV_DUAL_P2_00_L (REG_DVI_RSV_DUAL_P2_BASE + 0x00)
4894 #define REG_DVI_RSV_DUAL_P2_00_H (REG_DVI_RSV_DUAL_P2_BASE + 0x01)
4895 #define REG_DVI_RSV_DUAL_P2_01_L (REG_DVI_RSV_DUAL_P2_BASE + 0x02)
4896 #define REG_DVI_RSV_DUAL_P2_01_H (REG_DVI_RSV_DUAL_P2_BASE + 0x03)
4897 #define REG_DVI_RSV_DUAL_P2_02_L (REG_DVI_RSV_DUAL_P2_BASE + 0x04)
4898 #define REG_DVI_RSV_DUAL_P2_02_H (REG_DVI_RSV_DUAL_P2_BASE + 0x05)
4899 #define REG_DVI_RSV_DUAL_P2_03_L (REG_DVI_RSV_DUAL_P2_BASE + 0x06)
4900 #define REG_DVI_RSV_DUAL_P2_03_H (REG_DVI_RSV_DUAL_P2_BASE + 0x07)
4901 #define REG_DVI_RSV_DUAL_P2_04_L (REG_DVI_RSV_DUAL_P2_BASE + 0x08)
4902 #define REG_DVI_RSV_DUAL_P2_04_H (REG_DVI_RSV_DUAL_P2_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h646 #define REG_DVI_RSV_DUAL_P2_BASE 0x171700UL macro

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