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Searched refs:REG_DVI_RSV_DUAL_P1_BASE (Results 1 – 25 of 27) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h4357 #define REG_DVI_RSV_DUAL_P1_00_L (REG_DVI_RSV_DUAL_P1_BASE + 0x00)
4358 #define REG_DVI_RSV_DUAL_P1_00_H (REG_DVI_RSV_DUAL_P1_BASE + 0x01)
4359 #define REG_DVI_RSV_DUAL_P1_01_L (REG_DVI_RSV_DUAL_P1_BASE + 0x02)
4360 #define REG_DVI_RSV_DUAL_P1_01_H (REG_DVI_RSV_DUAL_P1_BASE + 0x03)
4361 #define REG_DVI_RSV_DUAL_P1_02_L (REG_DVI_RSV_DUAL_P1_BASE + 0x04)
4362 #define REG_DVI_RSV_DUAL_P1_02_H (REG_DVI_RSV_DUAL_P1_BASE + 0x05)
4363 #define REG_DVI_RSV_DUAL_P1_03_L (REG_DVI_RSV_DUAL_P1_BASE + 0x06)
4364 #define REG_DVI_RSV_DUAL_P1_03_H (REG_DVI_RSV_DUAL_P1_BASE + 0x07)
4365 #define REG_DVI_RSV_DUAL_P1_04_L (REG_DVI_RSV_DUAL_P1_BASE + 0x08)
4366 #define REG_DVI_RSV_DUAL_P1_04_H (REG_DVI_RSV_DUAL_P1_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h592 #define REG_DVI_RSV_DUAL_P1_BASE 0x171400UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h4359 #define REG_DVI_RSV_DUAL_P1_00_L (REG_DVI_RSV_DUAL_P1_BASE + 0x00)
4360 #define REG_DVI_RSV_DUAL_P1_00_H (REG_DVI_RSV_DUAL_P1_BASE + 0x01)
4361 #define REG_DVI_RSV_DUAL_P1_01_L (REG_DVI_RSV_DUAL_P1_BASE + 0x02)
4362 #define REG_DVI_RSV_DUAL_P1_01_H (REG_DVI_RSV_DUAL_P1_BASE + 0x03)
4363 #define REG_DVI_RSV_DUAL_P1_02_L (REG_DVI_RSV_DUAL_P1_BASE + 0x04)
4364 #define REG_DVI_RSV_DUAL_P1_02_H (REG_DVI_RSV_DUAL_P1_BASE + 0x05)
4365 #define REG_DVI_RSV_DUAL_P1_03_L (REG_DVI_RSV_DUAL_P1_BASE + 0x06)
4366 #define REG_DVI_RSV_DUAL_P1_03_H (REG_DVI_RSV_DUAL_P1_BASE + 0x07)
4367 #define REG_DVI_RSV_DUAL_P1_04_L (REG_DVI_RSV_DUAL_P1_BASE + 0x08)
4368 #define REG_DVI_RSV_DUAL_P1_04_H (REG_DVI_RSV_DUAL_P1_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h574 #define REG_DVI_RSV_DUAL_P1_BASE REG_DVI_RSV_DUAL_P0_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h4355 #define REG_DVI_RSV_DUAL_P1_00_L (REG_DVI_RSV_DUAL_P1_BASE + 0x00)
4356 #define REG_DVI_RSV_DUAL_P1_00_H (REG_DVI_RSV_DUAL_P1_BASE + 0x01)
4357 #define REG_DVI_RSV_DUAL_P1_01_L (REG_DVI_RSV_DUAL_P1_BASE + 0x02)
4358 #define REG_DVI_RSV_DUAL_P1_01_H (REG_DVI_RSV_DUAL_P1_BASE + 0x03)
4359 #define REG_DVI_RSV_DUAL_P1_02_L (REG_DVI_RSV_DUAL_P1_BASE + 0x04)
4360 #define REG_DVI_RSV_DUAL_P1_02_H (REG_DVI_RSV_DUAL_P1_BASE + 0x05)
4361 #define REG_DVI_RSV_DUAL_P1_03_L (REG_DVI_RSV_DUAL_P1_BASE + 0x06)
4362 #define REG_DVI_RSV_DUAL_P1_03_H (REG_DVI_RSV_DUAL_P1_BASE + 0x07)
4363 #define REG_DVI_RSV_DUAL_P1_04_L (REG_DVI_RSV_DUAL_P1_BASE + 0x08)
4364 #define REG_DVI_RSV_DUAL_P1_04_H (REG_DVI_RSV_DUAL_P1_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h552 #define REG_DVI_RSV_DUAL_P1_BASE 0x171400UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h4359 #define REG_DVI_RSV_DUAL_P1_00_L (REG_DVI_RSV_DUAL_P1_BASE + 0x00)
4360 #define REG_DVI_RSV_DUAL_P1_00_H (REG_DVI_RSV_DUAL_P1_BASE + 0x01)
4361 #define REG_DVI_RSV_DUAL_P1_01_L (REG_DVI_RSV_DUAL_P1_BASE + 0x02)
4362 #define REG_DVI_RSV_DUAL_P1_01_H (REG_DVI_RSV_DUAL_P1_BASE + 0x03)
4363 #define REG_DVI_RSV_DUAL_P1_02_L (REG_DVI_RSV_DUAL_P1_BASE + 0x04)
4364 #define REG_DVI_RSV_DUAL_P1_02_H (REG_DVI_RSV_DUAL_P1_BASE + 0x05)
4365 #define REG_DVI_RSV_DUAL_P1_03_L (REG_DVI_RSV_DUAL_P1_BASE + 0x06)
4366 #define REG_DVI_RSV_DUAL_P1_03_H (REG_DVI_RSV_DUAL_P1_BASE + 0x07)
4367 #define REG_DVI_RSV_DUAL_P1_04_L (REG_DVI_RSV_DUAL_P1_BASE + 0x08)
4368 #define REG_DVI_RSV_DUAL_P1_04_H (REG_DVI_RSV_DUAL_P1_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h576 #define REG_DVI_RSV_DUAL_P1_BASE REG_DVI_RSV_DUAL_P0_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h4355 #define REG_DVI_RSV_DUAL_P1_00_L (REG_DVI_RSV_DUAL_P1_BASE + 0x00)
4356 #define REG_DVI_RSV_DUAL_P1_00_H (REG_DVI_RSV_DUAL_P1_BASE + 0x01)
4357 #define REG_DVI_RSV_DUAL_P1_01_L (REG_DVI_RSV_DUAL_P1_BASE + 0x02)
4358 #define REG_DVI_RSV_DUAL_P1_01_H (REG_DVI_RSV_DUAL_P1_BASE + 0x03)
4359 #define REG_DVI_RSV_DUAL_P1_02_L (REG_DVI_RSV_DUAL_P1_BASE + 0x04)
4360 #define REG_DVI_RSV_DUAL_P1_02_H (REG_DVI_RSV_DUAL_P1_BASE + 0x05)
4361 #define REG_DVI_RSV_DUAL_P1_03_L (REG_DVI_RSV_DUAL_P1_BASE + 0x06)
4362 #define REG_DVI_RSV_DUAL_P1_03_H (REG_DVI_RSV_DUAL_P1_BASE + 0x07)
4363 #define REG_DVI_RSV_DUAL_P1_04_L (REG_DVI_RSV_DUAL_P1_BASE + 0x08)
4364 #define REG_DVI_RSV_DUAL_P1_04_H (REG_DVI_RSV_DUAL_P1_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h579 #define REG_DVI_RSV_DUAL_P1_BASE 0x171400UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h4359 #define REG_DVI_RSV_DUAL_P1_00_L (REG_DVI_RSV_DUAL_P1_BASE + 0x00)
4360 #define REG_DVI_RSV_DUAL_P1_00_H (REG_DVI_RSV_DUAL_P1_BASE + 0x01)
4361 #define REG_DVI_RSV_DUAL_P1_01_L (REG_DVI_RSV_DUAL_P1_BASE + 0x02)
4362 #define REG_DVI_RSV_DUAL_P1_01_H (REG_DVI_RSV_DUAL_P1_BASE + 0x03)
4363 #define REG_DVI_RSV_DUAL_P1_02_L (REG_DVI_RSV_DUAL_P1_BASE + 0x04)
4364 #define REG_DVI_RSV_DUAL_P1_02_H (REG_DVI_RSV_DUAL_P1_BASE + 0x05)
4365 #define REG_DVI_RSV_DUAL_P1_03_L (REG_DVI_RSV_DUAL_P1_BASE + 0x06)
4366 #define REG_DVI_RSV_DUAL_P1_03_H (REG_DVI_RSV_DUAL_P1_BASE + 0x07)
4367 #define REG_DVI_RSV_DUAL_P1_04_L (REG_DVI_RSV_DUAL_P1_BASE + 0x08)
4368 #define REG_DVI_RSV_DUAL_P1_04_H (REG_DVI_RSV_DUAL_P1_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h568 #define REG_DVI_RSV_DUAL_P1_BASE REG_DVI_RSV_DUAL_P0_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h4359 #define REG_DVI_RSV_DUAL_P1_00_L (REG_DVI_RSV_DUAL_P1_BASE + 0x00)
4360 #define REG_DVI_RSV_DUAL_P1_00_H (REG_DVI_RSV_DUAL_P1_BASE + 0x01)
4361 #define REG_DVI_RSV_DUAL_P1_01_L (REG_DVI_RSV_DUAL_P1_BASE + 0x02)
4362 #define REG_DVI_RSV_DUAL_P1_01_H (REG_DVI_RSV_DUAL_P1_BASE + 0x03)
4363 #define REG_DVI_RSV_DUAL_P1_02_L (REG_DVI_RSV_DUAL_P1_BASE + 0x04)
4364 #define REG_DVI_RSV_DUAL_P1_02_H (REG_DVI_RSV_DUAL_P1_BASE + 0x05)
4365 #define REG_DVI_RSV_DUAL_P1_03_L (REG_DVI_RSV_DUAL_P1_BASE + 0x06)
4366 #define REG_DVI_RSV_DUAL_P1_03_H (REG_DVI_RSV_DUAL_P1_BASE + 0x07)
4367 #define REG_DVI_RSV_DUAL_P1_04_L (REG_DVI_RSV_DUAL_P1_BASE + 0x08)
4368 #define REG_DVI_RSV_DUAL_P1_04_H (REG_DVI_RSV_DUAL_P1_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h574 #define REG_DVI_RSV_DUAL_P1_BASE REG_DVI_RSV_DUAL_P0_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h4355 #define REG_DVI_RSV_DUAL_P1_00_L (REG_DVI_RSV_DUAL_P1_BASE + 0x00)
4356 #define REG_DVI_RSV_DUAL_P1_00_H (REG_DVI_RSV_DUAL_P1_BASE + 0x01)
4357 #define REG_DVI_RSV_DUAL_P1_01_L (REG_DVI_RSV_DUAL_P1_BASE + 0x02)
4358 #define REG_DVI_RSV_DUAL_P1_01_H (REG_DVI_RSV_DUAL_P1_BASE + 0x03)
4359 #define REG_DVI_RSV_DUAL_P1_02_L (REG_DVI_RSV_DUAL_P1_BASE + 0x04)
4360 #define REG_DVI_RSV_DUAL_P1_02_H (REG_DVI_RSV_DUAL_P1_BASE + 0x05)
4361 #define REG_DVI_RSV_DUAL_P1_03_L (REG_DVI_RSV_DUAL_P1_BASE + 0x06)
4362 #define REG_DVI_RSV_DUAL_P1_03_H (REG_DVI_RSV_DUAL_P1_BASE + 0x07)
4363 #define REG_DVI_RSV_DUAL_P1_04_L (REG_DVI_RSV_DUAL_P1_BASE + 0x08)
4364 #define REG_DVI_RSV_DUAL_P1_04_H (REG_DVI_RSV_DUAL_P1_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h550 #define REG_DVI_RSV_DUAL_P1_BASE 0x171400UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h4356 #define REG_DVI_RSV_DUAL_P1_00_L (REG_DVI_RSV_DUAL_P1_BASE + 0x00)
4357 #define REG_DVI_RSV_DUAL_P1_00_H (REG_DVI_RSV_DUAL_P1_BASE + 0x01)
4358 #define REG_DVI_RSV_DUAL_P1_01_L (REG_DVI_RSV_DUAL_P1_BASE + 0x02)
4359 #define REG_DVI_RSV_DUAL_P1_01_H (REG_DVI_RSV_DUAL_P1_BASE + 0x03)
4360 #define REG_DVI_RSV_DUAL_P1_02_L (REG_DVI_RSV_DUAL_P1_BASE + 0x04)
4361 #define REG_DVI_RSV_DUAL_P1_02_H (REG_DVI_RSV_DUAL_P1_BASE + 0x05)
4362 #define REG_DVI_RSV_DUAL_P1_03_L (REG_DVI_RSV_DUAL_P1_BASE + 0x06)
4363 #define REG_DVI_RSV_DUAL_P1_03_H (REG_DVI_RSV_DUAL_P1_BASE + 0x07)
4364 #define REG_DVI_RSV_DUAL_P1_04_L (REG_DVI_RSV_DUAL_P1_BASE + 0x08)
4365 #define REG_DVI_RSV_DUAL_P1_04_H (REG_DVI_RSV_DUAL_P1_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h533 #define REG_DVI_RSV_DUAL_P1_BASE 0x171400UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h4355 #define REG_DVI_RSV_DUAL_P1_00_L (REG_DVI_RSV_DUAL_P1_BASE + 0x00)
4356 #define REG_DVI_RSV_DUAL_P1_00_H (REG_DVI_RSV_DUAL_P1_BASE + 0x01)
4357 #define REG_DVI_RSV_DUAL_P1_01_L (REG_DVI_RSV_DUAL_P1_BASE + 0x02)
4358 #define REG_DVI_RSV_DUAL_P1_01_H (REG_DVI_RSV_DUAL_P1_BASE + 0x03)
4359 #define REG_DVI_RSV_DUAL_P1_02_L (REG_DVI_RSV_DUAL_P1_BASE + 0x04)
4360 #define REG_DVI_RSV_DUAL_P1_02_H (REG_DVI_RSV_DUAL_P1_BASE + 0x05)
4361 #define REG_DVI_RSV_DUAL_P1_03_L (REG_DVI_RSV_DUAL_P1_BASE + 0x06)
4362 #define REG_DVI_RSV_DUAL_P1_03_H (REG_DVI_RSV_DUAL_P1_BASE + 0x07)
4363 #define REG_DVI_RSV_DUAL_P1_04_L (REG_DVI_RSV_DUAL_P1_BASE + 0x08)
4364 #define REG_DVI_RSV_DUAL_P1_04_H (REG_DVI_RSV_DUAL_P1_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h626 #define REG_DVI_RSV_DUAL_P1_BASE 0x171400UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h4357 #define REG_DVI_RSV_DUAL_P1_00_L (REG_DVI_RSV_DUAL_P1_BASE + 0x00)
4358 #define REG_DVI_RSV_DUAL_P1_00_H (REG_DVI_RSV_DUAL_P1_BASE + 0x01)
4359 #define REG_DVI_RSV_DUAL_P1_01_L (REG_DVI_RSV_DUAL_P1_BASE + 0x02)
4360 #define REG_DVI_RSV_DUAL_P1_01_H (REG_DVI_RSV_DUAL_P1_BASE + 0x03)
4361 #define REG_DVI_RSV_DUAL_P1_02_L (REG_DVI_RSV_DUAL_P1_BASE + 0x04)
4362 #define REG_DVI_RSV_DUAL_P1_02_H (REG_DVI_RSV_DUAL_P1_BASE + 0x05)
4363 #define REG_DVI_RSV_DUAL_P1_03_L (REG_DVI_RSV_DUAL_P1_BASE + 0x06)
4364 #define REG_DVI_RSV_DUAL_P1_03_H (REG_DVI_RSV_DUAL_P1_BASE + 0x07)
4365 #define REG_DVI_RSV_DUAL_P1_04_L (REG_DVI_RSV_DUAL_P1_BASE + 0x08)
4366 #define REG_DVI_RSV_DUAL_P1_04_H (REG_DVI_RSV_DUAL_P1_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h638 #define REG_DVI_RSV_DUAL_P1_BASE 0x171400UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h4357 #define REG_DVI_RSV_DUAL_P1_00_L (REG_DVI_RSV_DUAL_P1_BASE + 0x00)
4358 #define REG_DVI_RSV_DUAL_P1_00_H (REG_DVI_RSV_DUAL_P1_BASE + 0x01)
4359 #define REG_DVI_RSV_DUAL_P1_01_L (REG_DVI_RSV_DUAL_P1_BASE + 0x02)
4360 #define REG_DVI_RSV_DUAL_P1_01_H (REG_DVI_RSV_DUAL_P1_BASE + 0x03)
4361 #define REG_DVI_RSV_DUAL_P1_02_L (REG_DVI_RSV_DUAL_P1_BASE + 0x04)
4362 #define REG_DVI_RSV_DUAL_P1_02_H (REG_DVI_RSV_DUAL_P1_BASE + 0x05)
4363 #define REG_DVI_RSV_DUAL_P1_03_L (REG_DVI_RSV_DUAL_P1_BASE + 0x06)
4364 #define REG_DVI_RSV_DUAL_P1_03_H (REG_DVI_RSV_DUAL_P1_BASE + 0x07)
4365 #define REG_DVI_RSV_DUAL_P1_04_L (REG_DVI_RSV_DUAL_P1_BASE + 0x08)
4366 #define REG_DVI_RSV_DUAL_P1_04_H (REG_DVI_RSV_DUAL_P1_BASE + 0x09)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_hdmi.h4357 #define REG_DVI_RSV_DUAL_P1_00_L (REG_DVI_RSV_DUAL_P1_BASE + 0x00)
4358 #define REG_DVI_RSV_DUAL_P1_00_H (REG_DVI_RSV_DUAL_P1_BASE + 0x01)
4359 #define REG_DVI_RSV_DUAL_P1_01_L (REG_DVI_RSV_DUAL_P1_BASE + 0x02)
4360 #define REG_DVI_RSV_DUAL_P1_01_H (REG_DVI_RSV_DUAL_P1_BASE + 0x03)
4361 #define REG_DVI_RSV_DUAL_P1_02_L (REG_DVI_RSV_DUAL_P1_BASE + 0x04)
4362 #define REG_DVI_RSV_DUAL_P1_02_H (REG_DVI_RSV_DUAL_P1_BASE + 0x05)
4363 #define REG_DVI_RSV_DUAL_P1_03_L (REG_DVI_RSV_DUAL_P1_BASE + 0x06)
4364 #define REG_DVI_RSV_DUAL_P1_03_H (REG_DVI_RSV_DUAL_P1_BASE + 0x07)
4365 #define REG_DVI_RSV_DUAL_P1_04_L (REG_DVI_RSV_DUAL_P1_BASE + 0x08)
4366 #define REG_DVI_RSV_DUAL_P1_04_H (REG_DVI_RSV_DUAL_P1_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h643 #define REG_DVI_RSV_DUAL_P1_BASE 0x171400UL macro

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