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Searched refs:REG_DVI_DTOP_31_L (Results 1 – 25 of 32) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_hdmi.c2412 …if( (R2BYTE(REG_DVI_DTOP_16_L+u16bank_offset) & BIT(10)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offs… in Hal_DVI_IMMESWITCH_PS_SW_Path()
2420 …if( !(R2BYTE(REG_DVI_PS_00_L+u8reg_offset) & BIT(0)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offset) … in Hal_DVI_IMMESWITCH_PS_SW_Path()
2664 result = (R2BYTEMSK(REG_DVI_DTOP_31_L+u16bank_offset, 0x0070) & BIT(6)) ? TRUE : FALSE; in Hal_DVI_GetDEStableStatus()
3499 W2BYTEMSK(REG_DVI_DTOP_31_L, 0x0500, BMASK(15:8)); in Hal_HDMI_StablePolling()
3503 W2BYTEMSK(REG_DVI_DTOP_31_L, 0x0C00, BMASK(15:8)); in Hal_HDMI_StablePolling()
3509 if(!(R2BYTE(REG_DVI_DTOP_31_L) &BIT(6))) in Hal_HDMI_StablePolling()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_hdmi.c2412 …if( (R2BYTE(REG_DVI_DTOP_16_L+u16bank_offset) & BIT(10)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offs… in Hal_DVI_IMMESWITCH_PS_SW_Path()
2420 …if( !(R2BYTE(REG_DVI_PS_00_L+u8reg_offset) & BIT(0)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offset) … in Hal_DVI_IMMESWITCH_PS_SW_Path()
2664 result = (R2BYTEMSK(REG_DVI_DTOP_31_L+u16bank_offset, 0x0070) & BIT(6)) ? TRUE : FALSE; in Hal_DVI_GetDEStableStatus()
3499 W2BYTEMSK(REG_DVI_DTOP_31_L, 0x0500, BMASK(15:8)); in Hal_HDMI_StablePolling()
3503 W2BYTEMSK(REG_DVI_DTOP_31_L, 0x0C00, BMASK(15:8)); in Hal_HDMI_StablePolling()
3509 if(!(R2BYTE(REG_DVI_DTOP_31_L) &BIT(6))) in Hal_HDMI_StablePolling()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_hdmi.c2684 if(R2BYTE(REG_DVI_DTOP_31_L) & BIT(6)) in Hal_DVI_HF_adjust()
2874 …if( (R2BYTE(REG_DVI_DTOP_16_L+u16bank_offset) & BIT(10)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offs… in Hal_DVI_IMMESWITCH_PS_SW_Path()
2882 …if( !(R2BYTE(REG_DVI_PS_00_L+u8reg_offset) & BIT(0)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offset) … in Hal_DVI_IMMESWITCH_PS_SW_Path()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_hdmi.c3421 if(R2BYTE(REG_DVI_DTOP_31_L) & BIT(6)) in Hal_DVI_HF_adjust()
3611 …if( (R2BYTE(REG_DVI_DTOP_16_L+u16bank_offset) & BIT(10)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offs… in Hal_DVI_IMMESWITCH_PS_SW_Path()
3619 …if( !(R2BYTE(REG_DVI_PS_00_L+u8reg_offset) & BIT(0)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offset) … in Hal_DVI_IMMESWITCH_PS_SW_Path()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c5043 if(R2BYTE(REG_DVI_DTOP_31_L) & BIT(6)) in Hal_DVI_HF_adjust()
5229 …if( (R2BYTE(REG_DVI_DTOP_16_L+u16bank_offset) & BIT(10)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offs… in Hal_DVI_IMMESWITCH_PS_SW_Path()
5237 …if( !(R2BYTE(REG_DVI_PS_00_L+u8reg_offset) & BIT(0)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offset) … in Hal_DVI_IMMESWITCH_PS_SW_Path()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c5143 if(R2BYTE(REG_DVI_DTOP_31_L) & BIT(6)) in Hal_DVI_HF_adjust()
5329 …if( (R2BYTE(REG_DVI_DTOP_16_L+u16bank_offset) & BIT(10)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offs… in Hal_DVI_IMMESWITCH_PS_SW_Path()
5337 …if( !(R2BYTE(REG_DVI_PS_00_L+u8reg_offset) & BIT(0)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offset) … in Hal_DVI_IMMESWITCH_PS_SW_Path()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c5181 if(R2BYTE(REG_DVI_DTOP_31_L) & BIT(6)) in Hal_DVI_HF_adjust()
5371 …if( (R2BYTE(REG_DVI_DTOP_16_L+u16bank_offset) & BIT(10)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offs… in Hal_DVI_IMMESWITCH_PS_SW_Path()
5379 …if( !(R2BYTE(REG_DVI_PS_00_L+u8reg_offset) & BIT(0)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offset) … in Hal_DVI_IMMESWITCH_PS_SW_Path()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c5143 if(R2BYTE(REG_DVI_DTOP_31_L) & BIT(6)) in Hal_DVI_HF_adjust()
5329 …if( (R2BYTE(REG_DVI_DTOP_16_L+u16bank_offset) & BIT(10)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offs… in Hal_DVI_IMMESWITCH_PS_SW_Path()
5337 …if( !(R2BYTE(REG_DVI_PS_00_L+u8reg_offset) & BIT(0)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offset) … in Hal_DVI_IMMESWITCH_PS_SW_Path()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c5154 if(R2BYTE(REG_DVI_DTOP_31_L) & BIT(6)) in Hal_DVI_HF_adjust()
5344 …if( (R2BYTE(REG_DVI_DTOP_16_L+u16bank_offset) & BIT(10)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offs… in Hal_DVI_IMMESWITCH_PS_SW_Path()
5352 …if( !(R2BYTE(REG_DVI_PS_00_L+u8reg_offset) & BIT(0)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offset) … in Hal_DVI_IMMESWITCH_PS_SW_Path()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c5181 if(R2BYTE(REG_DVI_DTOP_31_L) & BIT(6)) in Hal_DVI_HF_adjust()
5371 …if( (R2BYTE(REG_DVI_DTOP_16_L+u16bank_offset) & BIT(10)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offs… in Hal_DVI_IMMESWITCH_PS_SW_Path()
5379 …if( !(R2BYTE(REG_DVI_PS_00_L+u8reg_offset) & BIT(0)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offset) … in Hal_DVI_IMMESWITCH_PS_SW_Path()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c5746 if(R2BYTE(REG_DVI_DTOP_31_L) & BIT(6)) in Hal_DVI_HF_adjust()
5932 …if( (R2BYTE(REG_DVI_DTOP_16_L+u16bank_offset) & BIT(10)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offs… in Hal_DVI_IMMESWITCH_PS_SW_Path()
5940 …if( !(R2BYTE(REG_DVI_PS_00_L+u8reg_offset) & BIT(0)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offset) … in Hal_DVI_IMMESWITCH_PS_SW_Path()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c5749 if(R2BYTE(REG_DVI_DTOP_31_L) & BIT(6)) in Hal_DVI_HF_adjust()
5935 …if( (R2BYTE(REG_DVI_DTOP_16_L+u16bank_offset) & BIT(10)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offs… in Hal_DVI_IMMESWITCH_PS_SW_Path()
5943 …if( !(R2BYTE(REG_DVI_PS_00_L+u8reg_offset) & BIT(0)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offset) … in Hal_DVI_IMMESWITCH_PS_SW_Path()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c5452 if(R2BYTE(REG_DVI_DTOP_31_L) & BIT(6)) in Hal_DVI_HF_adjust()
5642 …if( (R2BYTE(REG_DVI_DTOP_16_L+u16bank_offset) & BIT(10)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offs… in Hal_DVI_IMMESWITCH_PS_SW_Path()
5650 …if( !(R2BYTE(REG_DVI_PS_00_L+u8reg_offset) & BIT(0)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offset) … in Hal_DVI_IMMESWITCH_PS_SW_Path()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c5752 if(R2BYTE(REG_DVI_DTOP_31_L) & BIT(6)) in Hal_DVI_HF_adjust()
5938 …if( (R2BYTE(REG_DVI_DTOP_16_L+u16bank_offset) & BIT(10)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offs… in Hal_DVI_IMMESWITCH_PS_SW_Path()
5946 …if( !(R2BYTE(REG_DVI_PS_00_L+u8reg_offset) & BIT(0)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offset) … in Hal_DVI_IMMESWITCH_PS_SW_Path()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c5452 if(R2BYTE(REG_DVI_DTOP_31_L) & BIT(6)) in Hal_DVI_HF_adjust()
5642 …if( (R2BYTE(REG_DVI_DTOP_16_L+u16bank_offset) & BIT(10)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offs… in Hal_DVI_IMMESWITCH_PS_SW_Path()
5650 …if( !(R2BYTE(REG_DVI_PS_00_L+u8reg_offset) & BIT(0)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offset) … in Hal_DVI_IMMESWITCH_PS_SW_Path()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dhwreg_hdmi.h200 #define REG_DVI_DTOP_31_L (REG_DVI_DTOP_BASE + 0x62) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mustang/mhl/internal/
H A DhalMHL.c1750 if((R2BYTE(REG_DVI_DTOP_31_L) &BIT(6)) == BIT(6)) // DE stable in mhal_mhl_CDRModeMonitor()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maldives/mhl/internal/
H A DhalMHL.c1750 if((R2BYTE(REG_DVI_DTOP_31_L) &BIT(6)) == BIT(6)) // DE stable in mhal_mhl_CDRModeMonitor()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dhwreg_hdmi.h200 #define REG_DVI_DTOP_31_L (REG_DVI_DTOP_BASE + 0x62) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h200 #define REG_DVI_DTOP_31_L (REG_DVI_DTOP_BASE + 0x62) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h200 #define REG_DVI_DTOP_31_L (REG_DVI_DTOP_BASE + 0x62) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h200 #define REG_DVI_DTOP_31_L (REG_DVI_DTOP_BASE + 0x62) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h200 #define REG_DVI_DTOP_31_L (REG_DVI_DTOP_BASE + 0x62) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h200 #define REG_DVI_DTOP_31_L (REG_DVI_DTOP_BASE + 0x62) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h200 #define REG_DVI_DTOP_31_L (REG_DVI_DTOP_BASE + 0x62) macro

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