| /utopia/UTPA2-700.0.x/modules/hdmi/hal/mustang/mhl/internal/ |
| H A D | halMHL.c | 259 if((R2BYTE(REG_DVI_DTOP_2F_L) &BIT(0)) == BIT(0)) in _mhal_mhl_DviAutoEQSwitch()
270 W2BYTEMSK(REG_DVI_DTOP_2F_L, BIT(0), BIT(0)); // enable autoEQ controller in _mhal_mhl_DviAutoEQSwitch()
275 W2BYTEMSK(REG_DVI_DTOP_2F_L, 0, BIT(0)); // disable autoEQ controller in _mhal_mhl_DviAutoEQSwitch()
404 W2BYTEMSK(REG_DVI_DTOP_2F_L, 0, BMASK(15:4)| BMASK(3:2)); in _mhal_mhl_HdmiBypassModeSetting()
537 …W2BYTEMSK(REG_DVI_DTOP_2F_L, (MHL_DIGITAL_UNLOCK_RANGE << 4)| BMASK(3:2), BMASK(15:4)| BMASK(3:2)); in _mhal_mhl_Mhl24bitsModeSetting()
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/maldives/mhl/internal/ |
| H A D | halMHL.c | 259 if((R2BYTE(REG_DVI_DTOP_2F_L) &BIT(0)) == BIT(0)) in _mhal_mhl_DviAutoEQSwitch()
270 W2BYTEMSK(REG_DVI_DTOP_2F_L, BIT(0), BIT(0)); // enable autoEQ controller in _mhal_mhl_DviAutoEQSwitch()
275 W2BYTEMSK(REG_DVI_DTOP_2F_L, 0, BIT(0)); // disable autoEQ controller in _mhal_mhl_DviAutoEQSwitch()
404 W2BYTEMSK(REG_DVI_DTOP_2F_L, 0, BMASK(15:4)| BMASK(3:2)); in _mhal_mhl_HdmiBypassModeSetting()
537 …W2BYTEMSK(REG_DVI_DTOP_2F_L, (MHL_DIGITAL_UNLOCK_RANGE << 4)| BMASK(3:2), BMASK(15:4)| BMASK(3:2)); in _mhal_mhl_Mhl24bitsModeSetting()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/ |
| H A D | hwreg_hdmi.h | 196 #define REG_DVI_DTOP_2F_L (REG_DVI_DTOP_BASE + 0x5E) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/ |
| H A D | hwreg_hdmi.h | 196 #define REG_DVI_DTOP_2F_L (REG_DVI_DTOP_BASE + 0x5E) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/ |
| H A D | mhal_hdmi.c | 4461 MDrv_WriteByte(REG_DVI_DTOP_2F_L+u16bank_offset, 0x89); // enable auto EQ trigger in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_hdmi.c | 4399 MDrv_WriteByte(REG_DVI_DTOP_2F_L+u16bank_offset, 0x89); // enable auto EQ trigger in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/ |
| H A D | mhal_hdmi.c | 4461 MDrv_WriteByte(REG_DVI_DTOP_2F_L+u16bank_offset, 0x89); // enable auto EQ trigger in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_hdmi.c | 4601 MDrv_WriteByte(REG_DVI_DTOP_2F_L+u16bank_offset, 0x89); // enable auto EQ trigger in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_hdmi.c | 4601 MDrv_WriteByte(REG_DVI_DTOP_2F_L+u16bank_offset, 0x89); // enable auto EQ trigger in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | hwreg_hdmi.h | 196 #define REG_DVI_DTOP_2F_L (REG_DVI_DTOP_BASE + 0x5E) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | hwreg_hdmi.h | 196 #define REG_DVI_DTOP_2F_L (REG_DVI_DTOP_BASE + 0x5E) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | hwreg_hdmi.h | 196 #define REG_DVI_DTOP_2F_L (REG_DVI_DTOP_BASE + 0x5E) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | hwreg_hdmi.h | 196 #define REG_DVI_DTOP_2F_L (REG_DVI_DTOP_BASE + 0x5E) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | hwreg_hdmi.h | 196 #define REG_DVI_DTOP_2F_L (REG_DVI_DTOP_BASE + 0x5E) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | hwreg_hdmi.h | 196 #define REG_DVI_DTOP_2F_L (REG_DVI_DTOP_BASE + 0x5E) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/ |
| H A D | hwreg_hdmi.h | 196 #define REG_DVI_DTOP_2F_L (REG_DVI_DTOP_BASE + 0x5E) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | hwreg_hdmi.h | 196 #define REG_DVI_DTOP_2F_L (REG_DVI_DTOP_BASE + 0x5E) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | hwreg_hdmi.h | 196 #define REG_DVI_DTOP_2F_L (REG_DVI_DTOP_BASE + 0x5E) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | hwreg_hdmi.h | 196 #define REG_DVI_DTOP_2F_L (REG_DVI_DTOP_BASE + 0x5E) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | hwreg_hdmi.h | 196 #define REG_DVI_DTOP_2F_L (REG_DVI_DTOP_BASE + 0x5E) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | hwreg_hdmi.h | 196 #define REG_DVI_DTOP_2F_L (REG_DVI_DTOP_BASE + 0x5E) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/ |
| H A D | hwreg_hdmi.h | 196 #define REG_DVI_DTOP_2F_L (REG_DVI_DTOP_BASE + 0x5E) macro
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