| /utopia/UTPA2-700.0.x/modules/hdmi/hal/mustang/mhl/internal/ |
| H A D | halMHL.c | 453 W2BYTEMSK(REG_DVI_DTOP3_0E_L, BIT(4), BIT(4)); // auto clear phase accumulator in _mhal_mhl_HdmiBypassModeSetting()
462 W2BYTEMSK(REG_DVI_DTOP3_0E_L, 0, BIT(4)); // auto clear phase accumulator in _mhal_mhl_HdmiBypassModeSetting()
586 W2BYTEMSK(REG_DVI_DTOP3_0E_L, 0, BIT(4)); // auto clear phase accumulator in _mhal_mhl_Mhl24bitsModeSetting()
1687 W2BYTEMSK(REG_DVI_DTOP3_0E_L, BIT(4), BIT(4)); // clear accumulator in mhal_mhl_Accumulator_Clr()
1688 W2BYTEMSK(REG_DVI_DTOP3_0E_L, 0, BIT(4)); in mhal_mhl_Accumulator_Clr()
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/maldives/mhl/internal/ |
| H A D | halMHL.c | 453 W2BYTEMSK(REG_DVI_DTOP3_0E_L, BIT(4), BIT(4)); // auto clear phase accumulator in _mhal_mhl_HdmiBypassModeSetting()
462 W2BYTEMSK(REG_DVI_DTOP3_0E_L, 0, BIT(4)); // auto clear phase accumulator in _mhal_mhl_HdmiBypassModeSetting()
586 W2BYTEMSK(REG_DVI_DTOP3_0E_L, 0, BIT(4)); // auto clear phase accumulator in _mhal_mhl_Mhl24bitsModeSetting()
1687 W2BYTEMSK(REG_DVI_DTOP3_0E_L, BIT(4), BIT(4)); // clear accumulator in mhal_mhl_Accumulator_Clr()
1688 W2BYTEMSK(REG_DVI_DTOP3_0E_L, 0, BIT(4)); in mhal_mhl_Accumulator_Clr()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/ |
| H A D | mhal_hdmi.c | 2341 W2BYTEMSK(REG_DVI_DTOP3_0E_L, BIT(4), BIT(4)); // clear accumulator in Hal_DVI_Accumulator_Monitor()
2342 W2BYTEMSK(REG_DVI_DTOP3_0E_L, 0, BIT(4) ); in Hal_DVI_Accumulator_Monitor()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/ |
| H A D | mhal_hdmi.c | 2341 W2BYTEMSK(REG_DVI_DTOP3_0E_L, BIT(4), BIT(4)); // clear accumulator in Hal_DVI_Accumulator_Monitor()
2342 W2BYTEMSK(REG_DVI_DTOP3_0E_L, 0, BIT(4) ); in Hal_DVI_Accumulator_Monitor()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/ |
| H A D | hwreg_hdmi.h | 361 #define REG_DVI_DTOP3_0E_L (REG_DVI_DTOP3_BASE + 0x1C) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/ |
| H A D | hwreg_hdmi.h | 361 #define REG_DVI_DTOP3_0E_L (REG_DVI_DTOP3_BASE + 0x1C) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | hwreg_hdmi.h | 355 #define REG_DVI_DTOP3_0E_L (REG_DVI_DTOP3_BASE + 0x1C) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | hwreg_hdmi.h | 355 #define REG_DVI_DTOP3_0E_L (REG_DVI_DTOP3_BASE + 0x1C) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | hwreg_hdmi.h | 355 #define REG_DVI_DTOP3_0E_L (REG_DVI_DTOP3_BASE + 0x1C) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | hwreg_hdmi.h | 355 #define REG_DVI_DTOP3_0E_L (REG_DVI_DTOP3_BASE + 0x1C) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | hwreg_hdmi.h | 355 #define REG_DVI_DTOP3_0E_L (REG_DVI_DTOP3_BASE + 0x1C) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | hwreg_hdmi.h | 355 #define REG_DVI_DTOP3_0E_L (REG_DVI_DTOP3_BASE + 0x1C) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/ |
| H A D | hwreg_hdmi.h | 355 #define REG_DVI_DTOP3_0E_L (REG_DVI_DTOP3_BASE + 0x1C) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | hwreg_hdmi.h | 355 #define REG_DVI_DTOP3_0E_L (REG_DVI_DTOP3_BASE + 0x1C) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | hwreg_hdmi.h | 355 #define REG_DVI_DTOP3_0E_L (REG_DVI_DTOP3_BASE + 0x1C) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | hwreg_hdmi.h | 355 #define REG_DVI_DTOP3_0E_L (REG_DVI_DTOP3_BASE + 0x1C) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | hwreg_hdmi.h | 355 #define REG_DVI_DTOP3_0E_L (REG_DVI_DTOP3_BASE + 0x1C) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | hwreg_hdmi.h | 355 #define REG_DVI_DTOP3_0E_L (REG_DVI_DTOP3_BASE + 0x1C) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/ |
| H A D | hwreg_hdmi.h | 355 #define REG_DVI_DTOP3_0E_L (REG_DVI_DTOP3_BASE + 0x1C) macro
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