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Searched refs:REG_DVI_DTOP1_2F_L (Results 1 – 17 of 17) sorted by relevance

/utopia/UTPA2-700.0.x/modules/hdmi/hal/mustang/mhl/internal/
H A DhalMHL.c289 if((R2BYTE(REG_DVI_DTOP1_2F_L) &BIT(0)) == BIT(0)) in _mhal_mhl_DviAutoEQSwitch()
300 W2BYTEMSK(REG_DVI_DTOP1_2F_L, BIT(0), BIT(0)); // enable autoEQ controller in _mhal_mhl_DviAutoEQSwitch()
305 W2BYTEMSK(REG_DVI_DTOP1_2F_L, 0, BIT(0)); // disable autoEQ controller in _mhal_mhl_DviAutoEQSwitch()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maldives/mhl/internal/
H A DhalMHL.c289 if((R2BYTE(REG_DVI_DTOP1_2F_L) &BIT(0)) == BIT(0)) in _mhal_mhl_DviAutoEQSwitch()
300 W2BYTEMSK(REG_DVI_DTOP1_2F_L, BIT(0), BIT(0)); // enable autoEQ controller in _mhal_mhl_DviAutoEQSwitch()
305 W2BYTEMSK(REG_DVI_DTOP1_2F_L, 0, BIT(0)); // disable autoEQ controller in _mhal_mhl_DviAutoEQSwitch()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dhwreg_hdmi.h269 #define REG_DVI_DTOP1_2F_L (REG_DVI_DTOP1_BASE + 0x5E) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dhwreg_hdmi.h269 #define REG_DVI_DTOP1_2F_L (REG_DVI_DTOP1_BASE + 0x5E) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h265 #define REG_DVI_DTOP1_2F_L (REG_DVI_DTOP1_BASE + 0x5E) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h265 #define REG_DVI_DTOP1_2F_L (REG_DVI_DTOP1_BASE + 0x5E) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h265 #define REG_DVI_DTOP1_2F_L (REG_DVI_DTOP1_BASE + 0x5E) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h265 #define REG_DVI_DTOP1_2F_L (REG_DVI_DTOP1_BASE + 0x5E) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h265 #define REG_DVI_DTOP1_2F_L (REG_DVI_DTOP1_BASE + 0x5E) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h265 #define REG_DVI_DTOP1_2F_L (REG_DVI_DTOP1_BASE + 0x5E) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h265 #define REG_DVI_DTOP1_2F_L (REG_DVI_DTOP1_BASE + 0x5E) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h265 #define REG_DVI_DTOP1_2F_L (REG_DVI_DTOP1_BASE + 0x5E) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h265 #define REG_DVI_DTOP1_2F_L (REG_DVI_DTOP1_BASE + 0x5E) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h265 #define REG_DVI_DTOP1_2F_L (REG_DVI_DTOP1_BASE + 0x5E) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h265 #define REG_DVI_DTOP1_2F_L (REG_DVI_DTOP1_BASE + 0x5E) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h265 #define REG_DVI_DTOP1_2F_L (REG_DVI_DTOP1_BASE + 0x5E) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_hdmi.h265 #define REG_DVI_DTOP1_2F_L (REG_DVI_DTOP1_BASE + 0x5E) macro