| /utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/ |
| H A D | mhal_hdmi.c | 321 W2BYTE(REG_DVI_ATOP2_71_L, BIT(14)); in Hal_HDCP22_PollingWriteDone()
322 W2BYTE(REG_DVI_ATOP2_71_L, 0); in Hal_HDCP22_PollingWriteDone()
387 W2BYTE(REG_DVI_ATOP2_71_L, BIT(14)); in Hal_HDCP22_PollingReadDone()
388 W2BYTE(REG_DVI_ATOP2_71_L, 0); in Hal_HDCP22_PollingReadDone()
2490 case INPUT_PORT_DVI3: u16reg_add = REG_DVI_ATOP2_71_L; break; in Hal_DVI_irq_forcemode()
2510 case INPUT_PORT_DVI3: u16reg_add = REG_DVI_ATOP2_71_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/ |
| H A D | mhal_hdmi.c | 321 W2BYTE(REG_DVI_ATOP2_71_L, BIT(14)); in Hal_HDCP22_PollingWriteDone()
322 W2BYTE(REG_DVI_ATOP2_71_L, 0); in Hal_HDCP22_PollingWriteDone()
387 W2BYTE(REG_DVI_ATOP2_71_L, BIT(14)); in Hal_HDCP22_PollingReadDone()
388 W2BYTE(REG_DVI_ATOP2_71_L, 0); in Hal_HDCP22_PollingReadDone()
2490 case INPUT_PORT_DVI3: u16reg_add = REG_DVI_ATOP2_71_L; break; in Hal_DVI_irq_forcemode()
2510 case INPUT_PORT_DVI3: u16reg_add = REG_DVI_ATOP2_71_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/mustang/mhl/internal/ |
| H A D | halMHL.c | 996 W2BYTEMSK(REG_DVI_ATOP2_71_L, BIT(8), BIT(8)); in _mhal_mhl_ClockBigChangeFlag()
997 W2BYTEMSK(REG_DVI_ATOP2_71_L, 0, BIT(8)); in _mhal_mhl_ClockBigChangeFlag()
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/maldives/mhl/internal/ |
| H A D | halMHL.c | 996 W2BYTEMSK(REG_DVI_ATOP2_71_L, BIT(8), BIT(8)); in _mhal_mhl_ClockBigChangeFlag()
997 W2BYTEMSK(REG_DVI_ATOP2_71_L, 0, BIT(8)); in _mhal_mhl_ClockBigChangeFlag()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/ |
| H A D | hwreg_hdmi.h | 860 #define REG_DVI_ATOP2_71_L (REG_DVI_ATOP2_BASE + 0xE2) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/ |
| H A D | hwreg_hdmi.h | 860 #define REG_DVI_ATOP2_71_L (REG_DVI_ATOP2_BASE + 0xE2) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | hwreg_hdmi.h | 848 #define REG_DVI_ATOP2_71_L (REG_DVI_ATOP2_BASE + 0xE2) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | hwreg_hdmi.h | 848 #define REG_DVI_ATOP2_71_L (REG_DVI_ATOP2_BASE + 0xE2) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | hwreg_hdmi.h | 848 #define REG_DVI_ATOP2_71_L (REG_DVI_ATOP2_BASE + 0xE2) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | hwreg_hdmi.h | 848 #define REG_DVI_ATOP2_71_L (REG_DVI_ATOP2_BASE + 0xE2) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | hwreg_hdmi.h | 848 #define REG_DVI_ATOP2_71_L (REG_DVI_ATOP2_BASE + 0xE2) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | hwreg_hdmi.h | 848 #define REG_DVI_ATOP2_71_L (REG_DVI_ATOP2_BASE + 0xE2) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/ |
| H A D | hwreg_hdmi.h | 848 #define REG_DVI_ATOP2_71_L (REG_DVI_ATOP2_BASE + 0xE2) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | hwreg_hdmi.h | 848 #define REG_DVI_ATOP2_71_L (REG_DVI_ATOP2_BASE + 0xE2) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | hwreg_hdmi.h | 848 #define REG_DVI_ATOP2_71_L (REG_DVI_ATOP2_BASE + 0xE2) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | hwreg_hdmi.h | 848 #define REG_DVI_ATOP2_71_L (REG_DVI_ATOP2_BASE + 0xE2) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | hwreg_hdmi.h | 848 #define REG_DVI_ATOP2_71_L (REG_DVI_ATOP2_BASE + 0xE2) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | hwreg_hdmi.h | 848 #define REG_DVI_ATOP2_71_L (REG_DVI_ATOP2_BASE + 0xE2) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/ |
| H A D | hwreg_hdmi.h | 848 #define REG_DVI_ATOP2_71_L (REG_DVI_ATOP2_BASE + 0xE2) macro
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