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Searched refs:REG_DVI_ATOP2_60_L (Results 1 – 23 of 23) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_mux.c381 W2BYTEMSK(REG_DVI_ATOP2_60_L, 0xFFDF, 0xFFDF); // disable DVI2 PLL power in Hal_SC_mux_set_dvi_mux()
394 W2BYTE(REG_DVI_ATOP2_60_L, 0xFFFF); // disable DVI2 PLL power in Hal_SC_mux_set_dvi_mux()
414 W2BYTEMSK(REG_DVI_ATOP2_60_L, 0xFFDF, 0xFFDF); // disable DVI2 PLL power in Hal_SC_mux_set_dvi_mux()
427 W2BYTE(REG_DVI_ATOP2_60_L, 0xFFFF); // disable DVI2 PLL power in Hal_SC_mux_set_dvi_mux()
447 W2BYTE(REG_DVI_ATOP2_60_L, 0); // enable DVI2 PLL power in Hal_SC_mux_set_dvi_mux()
460 W2BYTE(REG_DVI_ATOP2_60_L, 0); // enable DVI2 PLL power in Hal_SC_mux_set_dvi_mux()
480 W2BYTEMSK(REG_DVI_ATOP2_60_L, 0xFFDF, 0xFFDF); // disable DVI2 PLL power in Hal_SC_mux_set_dvi_mux()
493 W2BYTE(REG_DVI_ATOP2_60_L, 0xFFFF); // disable DVI2 PLL power in Hal_SC_mux_set_dvi_mux()
513 W2BYTEMSK(REG_DVI_ATOP2_60_L, 0xFFDF, 0xFFDF); // disable DVI2 PLL power in Hal_SC_mux_set_dvi_mux()
526 W2BYTE(REG_DVI_ATOP2_60_L, 0xFFFF); // disable DVI2 PLL power in Hal_SC_mux_set_dvi_mux()
H A Dmhal_offline.c430 MS_U16 u16DVIATOP_60 = R2BYTE(REG_DVI_ATOP2_60_L); in Hal_XC_GetOffLineOfDVI2()
435 W2BYTE(REG_DVI_ATOP2_60_L, 0); // enable DVI2 PLL power in Hal_XC_GetOffLineOfDVI2()
451 W2BYTE(REG_DVI_ATOP2_60_L, u16DVIATOP_60); in Hal_XC_GetOffLineOfDVI2()
H A Dmhal_hdmi.c1099 W2BYTE(REG_DVI_ATOP2_60_L, 0x0000); // enable DVI2 PLL power in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_mux.c381 W2BYTEMSK(REG_DVI_ATOP2_60_L, 0xFFDF, 0xFFDF); // disable DVI2 PLL power in Hal_SC_mux_set_dvi_mux()
394 W2BYTE(REG_DVI_ATOP2_60_L, 0xFFFF); // disable DVI2 PLL power in Hal_SC_mux_set_dvi_mux()
414 W2BYTEMSK(REG_DVI_ATOP2_60_L, 0xFFDF, 0xFFDF); // disable DVI2 PLL power in Hal_SC_mux_set_dvi_mux()
427 W2BYTE(REG_DVI_ATOP2_60_L, 0xFFFF); // disable DVI2 PLL power in Hal_SC_mux_set_dvi_mux()
447 W2BYTE(REG_DVI_ATOP2_60_L, 0); // enable DVI2 PLL power in Hal_SC_mux_set_dvi_mux()
460 W2BYTE(REG_DVI_ATOP2_60_L, 0); // enable DVI2 PLL power in Hal_SC_mux_set_dvi_mux()
480 W2BYTEMSK(REG_DVI_ATOP2_60_L, 0xFFDF, 0xFFDF); // disable DVI2 PLL power in Hal_SC_mux_set_dvi_mux()
493 W2BYTE(REG_DVI_ATOP2_60_L, 0xFFFF); // disable DVI2 PLL power in Hal_SC_mux_set_dvi_mux()
513 W2BYTEMSK(REG_DVI_ATOP2_60_L, 0xFFDF, 0xFFDF); // disable DVI2 PLL power in Hal_SC_mux_set_dvi_mux()
526 W2BYTE(REG_DVI_ATOP2_60_L, 0xFFFF); // disable DVI2 PLL power in Hal_SC_mux_set_dvi_mux()
H A Dmhal_offline.c430 MS_U16 u16DVIATOP_60 = R2BYTE(REG_DVI_ATOP2_60_L); in Hal_XC_GetOffLineOfDVI2()
435 W2BYTE(REG_DVI_ATOP2_60_L, 0); // enable DVI2 PLL power in Hal_XC_GetOffLineOfDVI2()
451 W2BYTE(REG_DVI_ATOP2_60_L, u16DVIATOP_60); in Hal_XC_GetOffLineOfDVI2()
H A Dmhal_hdmi.c1099 W2BYTE(REG_DVI_ATOP2_60_L, 0x0000); // enable DVI2 PLL power in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mustang/mhl/internal/
H A DhalMHL.c806 W2BYTEMSK(REG_DVI_ATOP2_60_L, 0, BMASK(13:11));// data R-term in _mhal_mhl_RxRtermControl()
811 W2BYTEMSK(REG_DVI_ATOP2_60_L, BMASK(13:12), BMASK(13:11));// data R-term in _mhal_mhl_RxRtermControl()
816 W2BYTEMSK(REG_DVI_ATOP2_60_L, BMASK(13:11), BMASK(13:11));// data R-term in _mhal_mhl_RxRtermControl()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maldives/mhl/internal/
H A DhalMHL.c806 W2BYTEMSK(REG_DVI_ATOP2_60_L, 0, BMASK(13:11));// data R-term in _mhal_mhl_RxRtermControl()
811 W2BYTEMSK(REG_DVI_ATOP2_60_L, BMASK(13:12), BMASK(13:11));// data R-term in _mhal_mhl_RxRtermControl()
816 W2BYTEMSK(REG_DVI_ATOP2_60_L, BMASK(13:11), BMASK(13:11));// data R-term in _mhal_mhl_RxRtermControl()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dhwreg_hdmi.h836 #define REG_DVI_ATOP2_60_L (REG_DVI_ATOP2_BASE + 0xC0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dhwreg_hdmi.h836 #define REG_DVI_ATOP2_60_L (REG_DVI_ATOP2_BASE + 0xC0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h824 #define REG_DVI_ATOP2_60_L (REG_DVI_ATOP2_BASE + 0xC0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h824 #define REG_DVI_ATOP2_60_L (REG_DVI_ATOP2_BASE + 0xC0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h824 #define REG_DVI_ATOP2_60_L (REG_DVI_ATOP2_BASE + 0xC0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h824 #define REG_DVI_ATOP2_60_L (REG_DVI_ATOP2_BASE + 0xC0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h824 #define REG_DVI_ATOP2_60_L (REG_DVI_ATOP2_BASE + 0xC0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h824 #define REG_DVI_ATOP2_60_L (REG_DVI_ATOP2_BASE + 0xC0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h824 #define REG_DVI_ATOP2_60_L (REG_DVI_ATOP2_BASE + 0xC0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h824 #define REG_DVI_ATOP2_60_L (REG_DVI_ATOP2_BASE + 0xC0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h824 #define REG_DVI_ATOP2_60_L (REG_DVI_ATOP2_BASE + 0xC0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h824 #define REG_DVI_ATOP2_60_L (REG_DVI_ATOP2_BASE + 0xC0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h824 #define REG_DVI_ATOP2_60_L (REG_DVI_ATOP2_BASE + 0xC0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h824 #define REG_DVI_ATOP2_60_L (REG_DVI_ATOP2_BASE + 0xC0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_hdmi.h824 #define REG_DVI_ATOP2_60_L (REG_DVI_ATOP2_BASE + 0xC0) macro