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Searched refs:REG_DVI_ATOP1_74_L (Results 1 – 21 of 21) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_mux.c398 … MDrv_WriteByteMask(REG_DVI_ATOP1_74_L, 0x3F, 0x3F); //power off for Port B DVI DPLPHI/DPLPHQ in Hal_SC_mux_set_dvi_mux()
431 … MDrv_WriteByteMask(REG_DVI_ATOP1_74_L, 0x00, 0x3F); //power on for Port B DVI DPLPHI/DPLPHQ in Hal_SC_mux_set_dvi_mux()
464 … MDrv_WriteByteMask(REG_DVI_ATOP1_74_L, 0x3F, 0x3F); //power off for Port B DVI DPLPHI/DPLPHQ in Hal_SC_mux_set_dvi_mux()
497 … MDrv_WriteByteMask(REG_DVI_ATOP1_74_L, 0x3F, 0x3F); //power off for Port B DVI DPLPHI/DPLPHQ in Hal_SC_mux_set_dvi_mux()
530 … MDrv_WriteByteMask(REG_DVI_ATOP1_74_L, 0x3F, 0x3F); //power off for Port B DVI DPLPHI/DPLPHQ in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c1103 MDrv_WriteByteMask(REG_DVI_ATOP1_74_L, 0x00, 0x3F); //power on for Port B DVI DPLPHI/DPLPHQ in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_mux.c398 … MDrv_WriteByteMask(REG_DVI_ATOP1_74_L, 0x3F, 0x3F); //power off for Port B DVI DPLPHI/DPLPHQ in Hal_SC_mux_set_dvi_mux()
431 … MDrv_WriteByteMask(REG_DVI_ATOP1_74_L, 0x00, 0x3F); //power on for Port B DVI DPLPHI/DPLPHQ in Hal_SC_mux_set_dvi_mux()
464 … MDrv_WriteByteMask(REG_DVI_ATOP1_74_L, 0x3F, 0x3F); //power off for Port B DVI DPLPHI/DPLPHQ in Hal_SC_mux_set_dvi_mux()
497 … MDrv_WriteByteMask(REG_DVI_ATOP1_74_L, 0x3F, 0x3F); //power off for Port B DVI DPLPHI/DPLPHQ in Hal_SC_mux_set_dvi_mux()
530 … MDrv_WriteByteMask(REG_DVI_ATOP1_74_L, 0x3F, 0x3F); //power off for Port B DVI DPLPHI/DPLPHQ in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c1103 MDrv_WriteByteMask(REG_DVI_ATOP1_74_L, 0x00, 0x3F); //power on for Port B DVI DPLPHI/DPLPHQ in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mustang/mhl/internal/
H A DhalMHL.c435 …W2BYTEMSK(REG_DVI_ATOP1_74_L, 0, BMASK(5:0)); // [2:0]: power down DPLPHI, [5:3]: power down DPLPHQ in _mhal_mhl_HdmiBypassModeSetting()
568 …W2BYTEMSK(REG_DVI_ATOP1_74_L, BMASK(5:0), BMASK(5:0)); // [2:0]: power down DPLPHI, [5:3]: power d… in _mhal_mhl_Mhl24bitsModeSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maldives/mhl/internal/
H A DhalMHL.c435 …W2BYTEMSK(REG_DVI_ATOP1_74_L, 0, BMASK(5:0)); // [2:0]: power down DPLPHI, [5:3]: power down DPLPHQ in _mhal_mhl_HdmiBypassModeSetting()
568 …W2BYTEMSK(REG_DVI_ATOP1_74_L, BMASK(5:0), BMASK(5:0)); // [2:0]: power down DPLPHI, [5:3]: power d… in _mhal_mhl_Mhl24bitsModeSetting()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dhwreg_hdmi.h820 #define REG_DVI_ATOP1_74_L (REG_DVI_ATOP1_BASE + 0xE8) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dhwreg_hdmi.h820 #define REG_DVI_ATOP1_74_L (REG_DVI_ATOP1_BASE + 0xE8) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h812 #define REG_DVI_ATOP1_74_L (REG_DVI_ATOP1_BASE + 0xE8) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h812 #define REG_DVI_ATOP1_74_L (REG_DVI_ATOP1_BASE + 0xE8) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h812 #define REG_DVI_ATOP1_74_L (REG_DVI_ATOP1_BASE + 0xE8) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h812 #define REG_DVI_ATOP1_74_L (REG_DVI_ATOP1_BASE + 0xE8) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h812 #define REG_DVI_ATOP1_74_L (REG_DVI_ATOP1_BASE + 0xE8) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h812 #define REG_DVI_ATOP1_74_L (REG_DVI_ATOP1_BASE + 0xE8) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h812 #define REG_DVI_ATOP1_74_L (REG_DVI_ATOP1_BASE + 0xE8) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h812 #define REG_DVI_ATOP1_74_L (REG_DVI_ATOP1_BASE + 0xE8) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h812 #define REG_DVI_ATOP1_74_L (REG_DVI_ATOP1_BASE + 0xE8) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h812 #define REG_DVI_ATOP1_74_L (REG_DVI_ATOP1_BASE + 0xE8) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h812 #define REG_DVI_ATOP1_74_L (REG_DVI_ATOP1_BASE + 0xE8) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h812 #define REG_DVI_ATOP1_74_L (REG_DVI_ATOP1_BASE + 0xE8) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_hdmi.h812 #define REG_DVI_ATOP1_74_L (REG_DVI_ATOP1_BASE + 0xE8) macro