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Searched refs:REG_DVI_ATOP1_70_L (Results 1 – 19 of 19) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_hdmi.c2449 case INPUT_PORT_DVI1: u16reg_val = R2BYTEMSK(REG_DVI_ATOP1_70_L, irqbit); break; in Hal_DVI_irq_info()
2469 case INPUT_PORT_DVI1: u16reg_add = REG_DVI_ATOP1_70_L; break; in Hal_DVI_irq_mask()
3893 W2BYTEMSK(REG_DVI_ATOP1_70_L, bEnableIRQ? 0: BIT(14), BIT(14)); in Hal_HDCP_WriteDoneInterruptEnable()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_hdmi.c2449 case INPUT_PORT_DVI1: u16reg_val = R2BYTEMSK(REG_DVI_ATOP1_70_L, irqbit); break; in Hal_DVI_irq_info()
2469 case INPUT_PORT_DVI1: u16reg_add = REG_DVI_ATOP1_70_L; break; in Hal_DVI_irq_mask()
3893 W2BYTEMSK(REG_DVI_ATOP1_70_L, bEnableIRQ? 0: BIT(14), BIT(14)); in Hal_HDCP_WriteDoneInterruptEnable()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dhwreg_hdmi.h816 #define REG_DVI_ATOP1_70_L (REG_DVI_ATOP1_BASE + 0xE0) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mustang/mhl/internal/
H A DhalMHL.c960 bindex = ((R2BYTE(REG_DVI_ATOP1_70_L) &BIT(0)) ?TRUE: FALSE); in _mhal_mhl_ClockBigChangeFlag()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maldives/mhl/internal/
H A DhalMHL.c960 bindex = ((R2BYTE(REG_DVI_ATOP1_70_L) &BIT(0)) ?TRUE: FALSE); in _mhal_mhl_ClockBigChangeFlag()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dhwreg_hdmi.h816 #define REG_DVI_ATOP1_70_L (REG_DVI_ATOP1_BASE + 0xE0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h808 #define REG_DVI_ATOP1_70_L (REG_DVI_ATOP1_BASE + 0xE0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h808 #define REG_DVI_ATOP1_70_L (REG_DVI_ATOP1_BASE + 0xE0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h808 #define REG_DVI_ATOP1_70_L (REG_DVI_ATOP1_BASE + 0xE0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h808 #define REG_DVI_ATOP1_70_L (REG_DVI_ATOP1_BASE + 0xE0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h808 #define REG_DVI_ATOP1_70_L (REG_DVI_ATOP1_BASE + 0xE0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h808 #define REG_DVI_ATOP1_70_L (REG_DVI_ATOP1_BASE + 0xE0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h808 #define REG_DVI_ATOP1_70_L (REG_DVI_ATOP1_BASE + 0xE0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h808 #define REG_DVI_ATOP1_70_L (REG_DVI_ATOP1_BASE + 0xE0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h808 #define REG_DVI_ATOP1_70_L (REG_DVI_ATOP1_BASE + 0xE0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h808 #define REG_DVI_ATOP1_70_L (REG_DVI_ATOP1_BASE + 0xE0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h808 #define REG_DVI_ATOP1_70_L (REG_DVI_ATOP1_BASE + 0xE0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h808 #define REG_DVI_ATOP1_70_L (REG_DVI_ATOP1_BASE + 0xE0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_hdmi.h808 #define REG_DVI_ATOP1_70_L (REG_DVI_ATOP1_BASE + 0xE0) macro