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Searched refs:REG_DVI_ATOP1_60_L (Results 1 – 23 of 23) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_mux.c380 …W2BYTEMSK(REG_DVI_ATOP1_60_L, 0xFFDF, 0xFFDF); // disable DVI1 PLL power, DVIPLL regulator should … in Hal_SC_mux_set_dvi_mux()
393 W2BYTE(REG_DVI_ATOP1_60_L, 0xFFFF); // disable DVI1 PLL power in Hal_SC_mux_set_dvi_mux()
413 W2BYTE(REG_DVI_ATOP1_60_L, 0); // enable DVI1 PLL power in Hal_SC_mux_set_dvi_mux()
426 W2BYTE(REG_DVI_ATOP1_60_L, 0); // enable DVI1 PLL power in Hal_SC_mux_set_dvi_mux()
446 W2BYTEMSK(REG_DVI_ATOP1_60_L, 0xFFDF, 0xFFDF); // disable DVI1 PLL power in Hal_SC_mux_set_dvi_mux()
459 W2BYTE(REG_DVI_ATOP1_60_L, 0xFFFF); // disable DVI1 PLL power in Hal_SC_mux_set_dvi_mux()
479 W2BYTEMSK(REG_DVI_ATOP1_60_L, 0xFFDF, 0xFFDF); // disable DVI1 PLL power in Hal_SC_mux_set_dvi_mux()
492 W2BYTE(REG_DVI_ATOP1_60_L, 0xFFFF); // disable DVI1 PLL power in Hal_SC_mux_set_dvi_mux()
512 W2BYTEMSK(REG_DVI_ATOP1_60_L, 0xFFDF, 0xFFDF); // disable DVI1 PLL power in Hal_SC_mux_set_dvi_mux()
525 W2BYTE(REG_DVI_ATOP1_60_L, 0xFFFF); // disable DVI1 PLL power in Hal_SC_mux_set_dvi_mux()
H A Dmhal_offline.c396 MS_U16 u16DVIATOP_60 = R2BYTE(REG_DVI_ATOP1_60_L); in Hal_XC_GetOffLineOfDVI1()
401 W2BYTE(REG_DVI_ATOP1_60_L, 0); // enable DVI1 PLL power in Hal_XC_GetOffLineOfDVI1()
417 W2BYTE(REG_DVI_ATOP1_60_L, u16DVIATOP_60); in Hal_XC_GetOffLineOfDVI1()
H A Dmhal_hdmi.c1098 W2BYTE(REG_DVI_ATOP1_60_L, 0x0000); // enable DVI1 PLL power in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_mux.c380 …W2BYTEMSK(REG_DVI_ATOP1_60_L, 0xFFDF, 0xFFDF); // disable DVI1 PLL power, DVIPLL regulator should … in Hal_SC_mux_set_dvi_mux()
393 W2BYTE(REG_DVI_ATOP1_60_L, 0xFFFF); // disable DVI1 PLL power in Hal_SC_mux_set_dvi_mux()
413 W2BYTE(REG_DVI_ATOP1_60_L, 0); // enable DVI1 PLL power in Hal_SC_mux_set_dvi_mux()
426 W2BYTE(REG_DVI_ATOP1_60_L, 0); // enable DVI1 PLL power in Hal_SC_mux_set_dvi_mux()
446 W2BYTEMSK(REG_DVI_ATOP1_60_L, 0xFFDF, 0xFFDF); // disable DVI1 PLL power in Hal_SC_mux_set_dvi_mux()
459 W2BYTE(REG_DVI_ATOP1_60_L, 0xFFFF); // disable DVI1 PLL power in Hal_SC_mux_set_dvi_mux()
479 W2BYTEMSK(REG_DVI_ATOP1_60_L, 0xFFDF, 0xFFDF); // disable DVI1 PLL power in Hal_SC_mux_set_dvi_mux()
492 W2BYTE(REG_DVI_ATOP1_60_L, 0xFFFF); // disable DVI1 PLL power in Hal_SC_mux_set_dvi_mux()
512 W2BYTEMSK(REG_DVI_ATOP1_60_L, 0xFFDF, 0xFFDF); // disable DVI1 PLL power in Hal_SC_mux_set_dvi_mux()
525 W2BYTE(REG_DVI_ATOP1_60_L, 0xFFFF); // disable DVI1 PLL power in Hal_SC_mux_set_dvi_mux()
H A Dmhal_offline.c396 MS_U16 u16DVIATOP_60 = R2BYTE(REG_DVI_ATOP1_60_L); in Hal_XC_GetOffLineOfDVI1()
401 W2BYTE(REG_DVI_ATOP1_60_L, 0); // enable DVI1 PLL power in Hal_XC_GetOffLineOfDVI1()
417 W2BYTE(REG_DVI_ATOP1_60_L, u16DVIATOP_60); in Hal_XC_GetOffLineOfDVI1()
H A Dmhal_hdmi.c1098 W2BYTE(REG_DVI_ATOP1_60_L, 0x0000); // enable DVI1 PLL power in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mustang/mhl/internal/
H A DhalMHL.c432 W2BYTEMSK(REG_DVI_ATOP1_60_L, 0, BIT(7)); // power on DVI PLL in _mhal_mhl_HdmiBypassModeSetting()
434 W2BYTEMSK(REG_DVI_ATOP1_60_L, 0, BMASK(2:1)); // [2:0]: power down RD in _mhal_mhl_HdmiBypassModeSetting()
567 W2BYTEMSK(REG_DVI_ATOP1_60_L, BMASK(2:1), BMASK(2:1)); // [2:0]: power down RD in _mhal_mhl_Mhl24bitsModeSetting()
758 W2BYTEMSK(REG_DVI_ATOP1_60_L, 0, BMASK(13:11));// data R-term in _mhal_mhl_RxRtermControl()
763 W2BYTEMSK(REG_DVI_ATOP1_60_L, BMASK(13:12), BMASK(13:11));// data R-term in _mhal_mhl_RxRtermControl()
768 W2BYTEMSK(REG_DVI_ATOP1_60_L, BMASK(13:11), BMASK(13:11));// data R-term in _mhal_mhl_RxRtermControl()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maldives/mhl/internal/
H A DhalMHL.c432 W2BYTEMSK(REG_DVI_ATOP1_60_L, 0, BIT(7)); // power on DVI PLL in _mhal_mhl_HdmiBypassModeSetting()
434 W2BYTEMSK(REG_DVI_ATOP1_60_L, 0, BMASK(2:1)); // [2:0]: power down RD in _mhal_mhl_HdmiBypassModeSetting()
567 W2BYTEMSK(REG_DVI_ATOP1_60_L, BMASK(2:1), BMASK(2:1)); // [2:0]: power down RD in _mhal_mhl_Mhl24bitsModeSetting()
758 W2BYTEMSK(REG_DVI_ATOP1_60_L, 0, BMASK(13:11));// data R-term in _mhal_mhl_RxRtermControl()
763 W2BYTEMSK(REG_DVI_ATOP1_60_L, BMASK(13:12), BMASK(13:11));// data R-term in _mhal_mhl_RxRtermControl()
768 W2BYTEMSK(REG_DVI_ATOP1_60_L, BMASK(13:11), BMASK(13:11));// data R-term in _mhal_mhl_RxRtermControl()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dhwreg_hdmi.h802 #define REG_DVI_ATOP1_60_L (REG_DVI_ATOP1_BASE + 0xC0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dhwreg_hdmi.h802 #define REG_DVI_ATOP1_60_L (REG_DVI_ATOP1_BASE + 0xC0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h794 #define REG_DVI_ATOP1_60_L (REG_DVI_ATOP1_BASE + 0xC0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h794 #define REG_DVI_ATOP1_60_L (REG_DVI_ATOP1_BASE + 0xC0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h794 #define REG_DVI_ATOP1_60_L (REG_DVI_ATOP1_BASE + 0xC0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h794 #define REG_DVI_ATOP1_60_L (REG_DVI_ATOP1_BASE + 0xC0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h794 #define REG_DVI_ATOP1_60_L (REG_DVI_ATOP1_BASE + 0xC0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h794 #define REG_DVI_ATOP1_60_L (REG_DVI_ATOP1_BASE + 0xC0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h794 #define REG_DVI_ATOP1_60_L (REG_DVI_ATOP1_BASE + 0xC0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h794 #define REG_DVI_ATOP1_60_L (REG_DVI_ATOP1_BASE + 0xC0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h794 #define REG_DVI_ATOP1_60_L (REG_DVI_ATOP1_BASE + 0xC0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h794 #define REG_DVI_ATOP1_60_L (REG_DVI_ATOP1_BASE + 0xC0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h794 #define REG_DVI_ATOP1_60_L (REG_DVI_ATOP1_BASE + 0xC0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h794 #define REG_DVI_ATOP1_60_L (REG_DVI_ATOP1_BASE + 0xC0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_hdmi.h794 #define REG_DVI_ATOP1_60_L (REG_DVI_ATOP1_BASE + 0xC0) macro