Searched refs:REG_DAC_PLL_35_L (Results 1 – 8 of 8) sorted by relevance
| /utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/include/ |
| H A D | hwreg_dac.h | 137 #define REG_DAC_PLL_35_L (REG_DACPLL_BASE + 0x6A) macro
|
| /utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/include/ |
| H A D | hwreg_dac.h | 137 #define REG_DAC_PLL_35_L (REG_DACPLL_BASE + 0x6A) macro
|
| /utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/include/ |
| H A D | hwreg_dac.h | 137 #define REG_DAC_PLL_35_L (REG_DACPLL_BASE + 0x6A) macro
|
| /utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/include/ |
| H A D | hwreg_dac.h | 137 #define REG_DAC_PLL_35_L (REG_DACPLL_BASE + 0x6A) macro
|
| /utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/ |
| H A D | halDAC.c | 695 W1BYTE(REG_DAC_PLL_35_L, 0x02, 7:0); //synth_ssc_mode[0] = 0, synth_ssc_sync[1] = 1 in Hal_HDMITx_InitSeq()
|
| /utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/ |
| H A D | halDAC.c | 1115 W1BYTE(REG_DAC_PLL_35_L, 0x02, 7:0); //synth_ssc_mode[0] = 0, synth_ssc_sync[1] = 1 in Hal_HDMITx_InitSeq()
|
| /utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/ |
| H A D | halDAC.c | 1115 W1BYTE(REG_DAC_PLL_35_L, 0x02, 7:0); //synth_ssc_mode[0] = 0, synth_ssc_sync[1] = 1 in Hal_HDMITx_InitSeq()
|
| /utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/ |
| H A D | halDAC.c | 1115 W1BYTE(REG_DAC_PLL_35_L, 0x02, 7:0); //synth_ssc_mode[0] = 0, synth_ssc_sync[1] = 1 in Hal_HDMITx_InitSeq()
|