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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _HWREG_DAC_H_ 96 #define _HWREG_DAC_H_ 97 98 #include "MsCommon.h" 99 100 #define REG_DAC_BASE (0x101A00) 101 #define REG_HDGEN_BASE (0x103000) 102 #define REG_DACPLL_BASE (0x121100) 103 104 #define REG_DAC_00_L (REG_DAC_BASE + 0x00) 105 #define REG_DAC_00_H (REG_DAC_BASE + 0x01) 106 #define REG_DAC_01_L (REG_DAC_BASE + 0x02) 107 #define REG_DAC_01_H (REG_DAC_BASE + 0x03) 108 #define REG_DAC_02_L (REG_DAC_BASE + 0x04) 109 #define REG_DAC_02_H (REG_DAC_BASE + 0x05) 110 #define REG_DAC_03_L (REG_DAC_BASE + 0x06) 111 #define REG_DAC_03_H (REG_DAC_BASE + 0x07) 112 #define REG_DAC_04_L (REG_DAC_BASE + 0x08) 113 #define REG_DAC_04_H (REG_DAC_BASE + 0x09) 114 #define REG_DAC_05_L (REG_DAC_BASE + 0x0A) 115 #define REG_DAC_05_H (REG_DAC_BASE + 0x0B) 116 #define REG_DAC_06_L (REG_DAC_BASE + 0x0C) 117 #define REG_DAC_06_H (REG_DAC_BASE + 0x0D) 118 #define REG_DAC_07_L (REG_DAC_BASE + 0x0E) 119 #define REG_DAC_07_H (REG_DAC_BASE + 0x0F) 120 #define REG_DAC_08_L (REG_DAC_BASE + 0x10) 121 #define REG_DAC_08_H (REG_DAC_BASE + 0x11) 122 123 #define REG_DAC_PLL_15_L (REG_DACPLL_BASE + 0x2A) 124 #define REG_DAC_PLL_15_H (REG_DACPLL_BASE + 0x2B) 125 #define REG_DAC_PLL_16_L (REG_DACPLL_BASE + 0x2C) 126 #define REG_DAC_PLL_16_H (REG_DACPLL_BASE + 0x2D) 127 #define REG_DAC_PLL_17_L (REG_DACPLL_BASE + 0x2E) 128 #define REG_DAC_PLL_17_H (REG_DACPLL_BASE + 0x2F) 129 #define REG_DAC_PLL_31_L (REG_DACPLL_BASE + 0x62) 130 #define REG_DAC_PLL_31_H (REG_DACPLL_BASE + 0x63) 131 #define REG_DAC_PLL_32_L (REG_DACPLL_BASE + 0x64) 132 #define REG_DAC_PLL_32_H (REG_DACPLL_BASE + 0x65) 133 #define REG_DAC_PLL_33_L (REG_DACPLL_BASE + 0x66) 134 #define REG_DAC_PLL_33_H (REG_DACPLL_BASE + 0x67) 135 #define REG_DAC_PLL_34_L (REG_DACPLL_BASE + 0x68) 136 #define REG_DAC_PLL_34_H (REG_DACPLL_BASE + 0x69) 137 #define REG_DAC_PLL_35_L (REG_DACPLL_BASE + 0x6A) 138 #define REG_DAC_PLL_35_H (REG_DACPLL_BASE + 0x6B) 139 140 #define CLK_ODCLK_P 0x00 141 #define CLK_VEDAC_P 0x01 142 #define REG_CKG_DAC1 (0x59) 143 #define REG_CKG_DAC2 (0x59) 144 #define REG_HSYNC_VSYNC_EN (0x47) 145 #define REG_CKG_DAC1_DISABLE_MASK 0:0 146 #define REG_CKG_DAC2_DISABLE_MASK 8:8 147 #define REG_CKG_DAC1_MASK 3:2 148 #define REG_CKG_DAC2_MASK 11:10 149 #define REG_HD_DAT_CLK_INV (0x04) 150 #define REG_HD_DAT_CLK_INV_MSK 0:0 151 #define REG_HD_DAT_CLK_DLY (0x04) 152 #define REG_HD_DAT_CLK_DLY_MSK 7:4 153 #define REG_HD_DAC_OUT_SEL (0x05) 154 #define REG_HD_DAC_OUT_SEL_MSK 1:0 // src sel: [00]HD GEN, [01]VE out(CVBS+S), [10]test, [11]VE out(YUV) 155 #define REG_HD_DAC_SWAP_SEL (0x05) 156 #define REG_HD_DAC_SWAP_SEL_MSK 10:8 157 #define REG_EN_IDAC_HDR_MSK 0:0 158 #define REG_EN_IDAC_HDG_MSK 1:1 159 #define REG_EN_IDAC_HDB_MSK 2:2 160 161 #define REG_MODE_HD (0x08) 162 #define REG_MODE_HD_MSK 9:9 163 #define REG_MODE_SD (0x08) 164 #define REG_MODE_SD_MSK 10:10 165 166 #define REG_EN_IDAC_SDX (0x00) 167 #define REG_EN_IDAC_SDX_MSK 0:0 168 #define REG_EN_IDAC_SDY (0x00) 169 #define REG_EN_IDAC_SDY_MSK 1:1 170 #define REG_EN_IDAC_SDC (0x00) 171 #define REG_EN_IDAC_SDC_MSK 2:2 172 #define REG_EN_IDAC_REF (0x00) 173 #define REG_EN_IDAC_REF_MSK 4:4 174 #define REG_EN_IDAC_SEL_REXT_MSK 0:0 175 #define REG_EN_IDAC_HDCLK_MSK 5:5 176 177 178 #define REG_GCR_IDAC_GAINSD (0x00) 179 #define REG_GCR_IDAC_GAINSD_MSK 14:8 180 #define REG_EN_REF_IDAC_GAINSD (0x00) 181 #define REG_EN_REF_IDAC_GAINSD_MSK 15:15 182 183 #define REG_SD_DAT_CLK_INV (0x01) 184 #define REG_SD_DAT_CLK_INV_MSK 0:0 185 #define REG_SD_DAT_CLK_DLY (0x01) 186 #define REG_SD_DAT_CLK_DLY_MSK 7:4 187 188 #define REG_SD_DAC_OUT_SEL (0x02) 189 #define REG_SD_DAC_OUT_SEL_MSK 1:0 190 191 #define REG_SD_DAC_SWAP_SEL (0x02) 192 #define REG_SD_DAC_SWAP_SEL_MSK 10:8 193 #endif 194 195