xref: /utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/include/hwreg_dac.h (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)

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#ifndef _HWREG_DAC_H_
#define _HWREG_DAC_H_

#include "MsCommon.h"

#define REG_DAC_BASE        (0x101A00)
#define REG_HDGEN_BASE      (0x103000)
#define REG_DACPLL_BASE     (0x121100)

#define REG_DAC_00_L        (REG_DAC_BASE + 0x00)
#define REG_DAC_00_H        (REG_DAC_BASE + 0x01)
#define REG_DAC_01_L        (REG_DAC_BASE + 0x02)
#define REG_DAC_01_H        (REG_DAC_BASE + 0x03)
#define REG_DAC_02_L        (REG_DAC_BASE + 0x04)
#define REG_DAC_02_H        (REG_DAC_BASE + 0x05)
#define REG_DAC_03_L        (REG_DAC_BASE + 0x06)
#define REG_DAC_03_H        (REG_DAC_BASE + 0x07)
#define REG_DAC_04_L        (REG_DAC_BASE + 0x08)
#define REG_DAC_04_H        (REG_DAC_BASE + 0x09)
#define REG_DAC_05_L        (REG_DAC_BASE + 0x0A)
#define REG_DAC_05_H        (REG_DAC_BASE + 0x0B)
#define REG_DAC_06_L        (REG_DAC_BASE + 0x0C)
#define REG_DAC_06_H        (REG_DAC_BASE + 0x0D)
#define REG_DAC_07_L        (REG_DAC_BASE + 0x0E)
#define REG_DAC_07_H        (REG_DAC_BASE + 0x0F)
#define REG_DAC_08_L        (REG_DAC_BASE + 0x10)
#define REG_DAC_08_H        (REG_DAC_BASE + 0x11)

#define REG_DAC_PLL_15_L    (REG_DACPLL_BASE + 0x2A)
#define REG_DAC_PLL_15_H    (REG_DACPLL_BASE + 0x2B)
#define REG_DAC_PLL_16_L    (REG_DACPLL_BASE + 0x2C)
#define REG_DAC_PLL_16_H    (REG_DACPLL_BASE + 0x2D)
#define REG_DAC_PLL_17_L    (REG_DACPLL_BASE + 0x2E)
#define REG_DAC_PLL_17_H    (REG_DACPLL_BASE + 0x2F)
#define REG_DAC_PLL_31_L    (REG_DACPLL_BASE + 0x62)
#define REG_DAC_PLL_31_H    (REG_DACPLL_BASE + 0x63)
#define REG_DAC_PLL_32_L    (REG_DACPLL_BASE + 0x64)
#define REG_DAC_PLL_32_H    (REG_DACPLL_BASE + 0x65)
#define REG_DAC_PLL_33_L    (REG_DACPLL_BASE + 0x66)
#define REG_DAC_PLL_33_H    (REG_DACPLL_BASE + 0x67)
#define REG_DAC_PLL_34_L    (REG_DACPLL_BASE + 0x68)
#define REG_DAC_PLL_34_H    (REG_DACPLL_BASE + 0x69)
#define REG_DAC_PLL_35_L    (REG_DACPLL_BASE + 0x6A)
#define REG_DAC_PLL_35_H    (REG_DACPLL_BASE + 0x6B)

#define CLK_ODCLK_P                 0x00
#define CLK_VEDAC_P                 0x01
#define REG_CKG_DAC1                (0x59)
#define REG_CKG_DAC2                (0x59)
#define REG_HSYNC_VSYNC_EN       	(0x47)
#define REG_CKG_DAC1_DISABLE_MASK           0:0
#define REG_CKG_DAC2_DISABLE_MASK           8:8
#define REG_CKG_DAC1_MASK           3:2
#define REG_CKG_DAC2_MASK           11:10
#define REG_HD_DAT_CLK_INV          (0x04)
#define REG_HD_DAT_CLK_INV_MSK      0:0
#define REG_HD_DAT_CLK_DLY          (0x04)
#define REG_HD_DAT_CLK_DLY_MSK      7:4
#define REG_HD_DAC_OUT_SEL          (0x05)
#define REG_HD_DAC_OUT_SEL_MSK      1:0  // src sel: [00]HD GEN, [01]VE out(CVBS+S), [10]test, [11]VE out(YUV)
#define REG_HD_DAC_SWAP_SEL         (0x05)
#define REG_HD_DAC_SWAP_SEL_MSK     10:8
#define REG_EN_IDAC_HDR_MSK         0:0
#define REG_EN_IDAC_HDG_MSK         1:1
#define REG_EN_IDAC_HDB_MSK         2:2

#define REG_MODE_HD                 (0x08)
#define REG_MODE_HD_MSK             9:9
#define REG_MODE_SD                 (0x08)
#define REG_MODE_SD_MSK             10:10

#define REG_EN_IDAC_SDX             (0x00)
#define REG_EN_IDAC_SDX_MSK         0:0
#define REG_EN_IDAC_SDY             (0x00)
#define REG_EN_IDAC_SDY_MSK         1:1
#define REG_EN_IDAC_SDC             (0x00)
#define REG_EN_IDAC_SDC_MSK         2:2
#define REG_EN_IDAC_REF             (0x00)
#define REG_EN_IDAC_REF_MSK         4:4
#define REG_EN_IDAC_SEL_REXT_MSK    0:0
#define REG_EN_IDAC_HDCLK_MSK       5:5


#define REG_GCR_IDAC_GAINSD         (0x00)
#define REG_GCR_IDAC_GAINSD_MSK     14:8
#define REG_EN_REF_IDAC_GAINSD      (0x00)
#define REG_EN_REF_IDAC_GAINSD_MSK  15:15

#define REG_SD_DAT_CLK_INV          (0x01)
#define REG_SD_DAT_CLK_INV_MSK      0:0
#define REG_SD_DAT_CLK_DLY          (0x01)
#define REG_SD_DAT_CLK_DLY_MSK      7:4

#define REG_SD_DAC_OUT_SEL          (0x02)
#define REG_SD_DAC_OUT_SEL_MSK      1:0

#define REG_SD_DAC_SWAP_SEL         (0x02)
#define REG_SD_DAC_SWAP_SEL_MSK     10:8
#endif