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Searched refs:REG_DAC_PLL_34_L (Results 1 – 8 of 8) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/include/
H A Dhwreg_dac.h135 #define REG_DAC_PLL_34_L (REG_DACPLL_BASE + 0x68) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/include/
H A Dhwreg_dac.h135 #define REG_DAC_PLL_34_L (REG_DACPLL_BASE + 0x68) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/include/
H A Dhwreg_dac.h135 #define REG_DAC_PLL_34_L (REG_DACPLL_BASE + 0x68) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/include/
H A Dhwreg_dac.h135 #define REG_DAC_PLL_34_L (REG_DACPLL_BASE + 0x68) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/
H A DhalDAC.c699 W1BYTE(REG_DAC_PLL_34_L, 0x00, 7:0); //synth_ssc_span[13:0]=445 in Hal_HDMITx_InitSeq()
/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/
H A DhalDAC.c1119 W1BYTE(REG_DAC_PLL_34_L, 0x00, 7:0); //synth_ssc_span[13:0]=445 in Hal_HDMITx_InitSeq()
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/
H A DhalDAC.c1119 W1BYTE(REG_DAC_PLL_34_L, 0x00, 7:0); //synth_ssc_span[13:0]=445 in Hal_HDMITx_InitSeq()
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/
H A DhalDAC.c1119 W1BYTE(REG_DAC_PLL_34_L, 0x00, 7:0); //synth_ssc_span[13:0]=445 in Hal_HDMITx_InitSeq()