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Searched refs:REG_C_IRQ_MASK (Results 1 – 25 of 32) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/irq/hal/M7821/irq/
H A DregIRQ.h201 #define REG_C_IRQ_MASK REG_FRC_C_IRQ_MASK macro
222 #define REG_C_IRQ_MASK REG_AEON_C_IRQ_MASK macro
247 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
273 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
297 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
320 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
344 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
367 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
H A DhalIRQ.c625 reg = REG_C_IRQ_MASK; in _HAL_IRQ_Enable()
760 _u32IRQ_Msk = _IRQ_Read4Byte(REG_C_IRQ_MASK); in HAL_IRQ_MaskAll()
764 _IRQ_Write4Byte(REG_C_IRQ_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
771 _IRQ_Write4Byte(REG_C_IRQ_MASK, 0); in HAL_IRQ_MaskAll()
780 _IRQ_Write4Byte(REG_C_IRQ_MASK, _u32IRQ_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/macan/irq/
H A DregIRQ.h201 #define REG_C_IRQ_MASK REG_FRC_C_IRQ_MASK macro
222 #define REG_C_IRQ_MASK REG_AEON_C_IRQ_MASK macro
247 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
273 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
297 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
320 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
344 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
367 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
H A DhalIRQ.c619 reg = REG_C_IRQ_MASK; in _HAL_IRQ_Enable()
753 _u32IRQ_Msk = _IRQ_Read4Byte(REG_C_IRQ_MASK); in HAL_IRQ_MaskAll()
757 _IRQ_Write4Byte(REG_C_IRQ_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
764 _IRQ_Write4Byte(REG_C_IRQ_MASK, 0); in HAL_IRQ_MaskAll()
773 _IRQ_Write4Byte(REG_C_IRQ_MASK, _u32IRQ_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/maserati/irq/
H A DregIRQ.h201 #define REG_C_IRQ_MASK REG_FRC_C_IRQ_MASK macro
222 #define REG_C_IRQ_MASK REG_AEON_C_IRQ_MASK macro
247 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
273 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
297 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
320 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
344 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
H A DhalIRQ.c623 reg = REG_C_IRQ_MASK; in _HAL_IRQ_Enable()
758 _u32IRQ_Msk = _IRQ_Read4Byte(REG_C_IRQ_MASK); in HAL_IRQ_MaskAll()
762 _IRQ_Write4Byte(REG_C_IRQ_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
769 _IRQ_Write4Byte(REG_C_IRQ_MASK, 0); in HAL_IRQ_MaskAll()
778 _IRQ_Write4Byte(REG_C_IRQ_MASK, _u32IRQ_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/manhattan/irq/
H A DregIRQ.h201 #define REG_C_IRQ_MASK REG_FRC_C_IRQ_MASK macro
222 #define REG_C_IRQ_MASK REG_AEON_C_IRQ_MASK macro
247 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
273 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
297 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
320 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
344 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
H A DhalIRQ.c619 reg = REG_C_IRQ_MASK; in _HAL_IRQ_Enable()
754 _u32IRQ_Msk = _IRQ_Read4Byte(REG_C_IRQ_MASK); in HAL_IRQ_MaskAll()
758 _IRQ_Write4Byte(REG_C_IRQ_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
765 _IRQ_Write4Byte(REG_C_IRQ_MASK, 0); in HAL_IRQ_MaskAll()
774 _IRQ_Write4Byte(REG_C_IRQ_MASK, _u32IRQ_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/maxim/irq/
H A DregIRQ.h201 #define REG_C_IRQ_MASK REG_FRC_C_IRQ_MASK macro
222 #define REG_C_IRQ_MASK REG_AEON_C_IRQ_MASK macro
247 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
273 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
297 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
320 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
344 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
H A DhalIRQ.c623 reg = REG_C_IRQ_MASK; in _HAL_IRQ_Enable()
758 _u32IRQ_Msk = _IRQ_Read4Byte(REG_C_IRQ_MASK); in HAL_IRQ_MaskAll()
762 _IRQ_Write4Byte(REG_C_IRQ_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
769 _IRQ_Write4Byte(REG_C_IRQ_MASK, 0); in HAL_IRQ_MaskAll()
778 _IRQ_Write4Byte(REG_C_IRQ_MASK, _u32IRQ_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/M7621/irq/
H A DregIRQ.h201 #define REG_C_IRQ_MASK REG_FRC_C_IRQ_MASK macro
222 #define REG_C_IRQ_MASK REG_AEON_C_IRQ_MASK macro
247 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
273 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
297 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
320 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
344 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
H A DhalIRQ.c623 reg = REG_C_IRQ_MASK; in _HAL_IRQ_Enable()
758 _u32IRQ_Msk = _IRQ_Read4Byte(REG_C_IRQ_MASK); in HAL_IRQ_MaskAll()
762 _IRQ_Write4Byte(REG_C_IRQ_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
769 _IRQ_Write4Byte(REG_C_IRQ_MASK, 0); in HAL_IRQ_MaskAll()
778 _IRQ_Write4Byte(REG_C_IRQ_MASK, _u32IRQ_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/mustang/irq/
H A DregIRQ.h155 #define REG_C_IRQ_MASK REG_AEON_C_IRQ_MASK macro
172 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
190 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
206 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
222 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
H A DhalIRQ.c429 reg = REG_C_IRQ_MASK; in _HAL_IRQ_Enable()
541 _u32IRQ_Msk = _IRQ_Read4Byte(REG_C_IRQ_MASK); in HAL_IRQ_MaskAll()
545 _IRQ_Write4Byte(REG_C_IRQ_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
552 _IRQ_Write4Byte(REG_C_IRQ_MASK, 0); in HAL_IRQ_MaskAll()
561 _IRQ_Write4Byte(REG_C_IRQ_MASK, _u32IRQ_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/maldives/irq/
H A DregIRQ.h155 #define REG_C_IRQ_MASK REG_AEON_C_IRQ_MASK macro
172 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
190 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
206 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
222 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
H A DhalIRQ.c429 reg = REG_C_IRQ_MASK; in _HAL_IRQ_Enable()
541 _u32IRQ_Msk = _IRQ_Read4Byte(REG_C_IRQ_MASK); in HAL_IRQ_MaskAll()
545 _IRQ_Write4Byte(REG_C_IRQ_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
552 _IRQ_Write4Byte(REG_C_IRQ_MASK, 0); in HAL_IRQ_MaskAll()
561 _IRQ_Write4Byte(REG_C_IRQ_MASK, _u32IRQ_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/mainz/irq/
H A DhalIRQ.c428 reg = REG_C_IRQ_MASK; in _HAL_IRQ_Enable()
545 _u32IRQ_Msk = _IRQ_Read4Byte(REG_C_IRQ_MASK); in HAL_IRQ_MaskAll()
549 _IRQ_Write4Byte(REG_C_IRQ_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
556 _IRQ_Write4Byte(REG_C_IRQ_MASK, 0); in HAL_IRQ_MaskAll()
565 _IRQ_Write4Byte(REG_C_IRQ_MASK, _u32IRQ_Msk); in HAL_IRQ_Restore()
H A DregIRQ.h146 #define REG_C_IRQ_MASK REG_AEON_C_IRQ_MASK macro
162 #define REG_C_IRQ_MASK REG_MIPS_C_IRQ_MASK macro
/utopia/UTPA2-700.0.x/modules/irq/hal/messi/irq/
H A DhalIRQ.c428 reg = REG_C_IRQ_MASK; in _HAL_IRQ_Enable()
545 _u32IRQ_Msk = _IRQ_Read4Byte(REG_C_IRQ_MASK); in HAL_IRQ_MaskAll()
549 _IRQ_Write4Byte(REG_C_IRQ_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
556 _IRQ_Write4Byte(REG_C_IRQ_MASK, 0); in HAL_IRQ_MaskAll()
565 _IRQ_Write4Byte(REG_C_IRQ_MASK, _u32IRQ_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/mooney/irq/
H A DhalIRQ.c428 reg = REG_C_IRQ_MASK; in _HAL_IRQ_Enable()
545 _u32IRQ_Msk = _IRQ_Read4Byte(REG_C_IRQ_MASK); in HAL_IRQ_MaskAll()
549 _IRQ_Write4Byte(REG_C_IRQ_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
556 _IRQ_Write4Byte(REG_C_IRQ_MASK, 0); in HAL_IRQ_MaskAll()
565 _IRQ_Write4Byte(REG_C_IRQ_MASK, _u32IRQ_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/k6/irq/
H A DhalIRQ.c570 reg = REG_C_IRQ_MASK; in _HAL_IRQ_Enable()
698 _u32IRQ_Msk = _IRQ_Read4Byte(REG_C_IRQ_MASK); in HAL_IRQ_MaskAll()
702 _IRQ_Write4Byte(REG_C_IRQ_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
709 _IRQ_Write4Byte(REG_C_IRQ_MASK, 0); in HAL_IRQ_MaskAll()
718 _IRQ_Write4Byte(REG_C_IRQ_MASK, _u32IRQ_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/k6lite/irq/
H A DhalIRQ.c570 reg = REG_C_IRQ_MASK; in _HAL_IRQ_Enable()
698 _u32IRQ_Msk = _IRQ_Read4Byte(REG_C_IRQ_MASK); in HAL_IRQ_MaskAll()
702 _IRQ_Write4Byte(REG_C_IRQ_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
709 _IRQ_Write4Byte(REG_C_IRQ_MASK, 0); in HAL_IRQ_MaskAll()
718 _IRQ_Write4Byte(REG_C_IRQ_MASK, _u32IRQ_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/kano/irq/
H A DhalIRQ.c570 reg = REG_C_IRQ_MASK; in _HAL_IRQ_Enable()
698 _u32IRQ_Msk = _IRQ_Read4Byte(REG_C_IRQ_MASK); in HAL_IRQ_MaskAll()
702 _IRQ_Write4Byte(REG_C_IRQ_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
709 _IRQ_Write4Byte(REG_C_IRQ_MASK, 0); in HAL_IRQ_MaskAll()
718 _IRQ_Write4Byte(REG_C_IRQ_MASK, _u32IRQ_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/k7u/irq/
H A DhalIRQ.c570 reg = REG_C_IRQ_MASK; in _HAL_IRQ_Enable()
698 _u32IRQ_Msk = _IRQ_Read4Byte(REG_C_IRQ_MASK); in HAL_IRQ_MaskAll()
702 _IRQ_Write4Byte(REG_C_IRQ_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
709 _IRQ_Write4Byte(REG_C_IRQ_MASK, 0); in HAL_IRQ_MaskAll()
718 _IRQ_Write4Byte(REG_C_IRQ_MASK, _u32IRQ_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/curry/irq/
H A DhalIRQ.c570 reg = REG_C_IRQ_MASK; in _HAL_IRQ_Enable()
698 _u32IRQ_Msk = _IRQ_Read4Byte(REG_C_IRQ_MASK); in HAL_IRQ_MaskAll()
702 _IRQ_Write4Byte(REG_C_IRQ_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
709 _IRQ_Write4Byte(REG_C_IRQ_MASK, 0); in HAL_IRQ_MaskAll()
718 _IRQ_Write4Byte(REG_C_IRQ_MASK, _u32IRQ_Msk); in HAL_IRQ_Restore()

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