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Searched refs:REG_C_IRQ_EXP_MASK (Results 1 – 25 of 32) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/irq/hal/M7821/irq/
H A DregIRQ.h212 #define REG_C_IRQ_EXP_MASK REG_FRC_C_IRQ_EXP_MASK macro
233 #define REG_C_IRQ_EXP_MASK REG_AEON_C_IRQ_EXP_MASK macro
258 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
284 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
308 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
331 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
355 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
378 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
H A DhalIRQ.c642 reg = REG_C_IRQ_EXP_MASK; in _HAL_IRQ_Enable()
762 _u32IRQExp_Msk = _IRQ_Read4Byte(REG_C_IRQ_EXP_MASK); in HAL_IRQ_MaskAll()
766 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
773 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, 0); in HAL_IRQ_MaskAll()
782 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, _u32IRQExp_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/macan/irq/
H A DregIRQ.h212 #define REG_C_IRQ_EXP_MASK REG_FRC_C_IRQ_EXP_MASK macro
233 #define REG_C_IRQ_EXP_MASK REG_AEON_C_IRQ_EXP_MASK macro
258 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
284 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
308 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
331 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
355 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
378 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
H A DhalIRQ.c636 reg = REG_C_IRQ_EXP_MASK; in _HAL_IRQ_Enable()
755 _u32IRQExp_Msk = _IRQ_Read4Byte(REG_C_IRQ_EXP_MASK); in HAL_IRQ_MaskAll()
759 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
766 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, 0); in HAL_IRQ_MaskAll()
775 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, _u32IRQExp_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/maserati/irq/
H A DregIRQ.h212 #define REG_C_IRQ_EXP_MASK REG_FRC_C_IRQ_EXP_MASK macro
233 #define REG_C_IRQ_EXP_MASK REG_AEON_C_IRQ_EXP_MASK macro
258 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
284 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
308 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
331 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
355 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
H A DhalIRQ.c640 reg = REG_C_IRQ_EXP_MASK; in _HAL_IRQ_Enable()
760 _u32IRQExp_Msk = _IRQ_Read4Byte(REG_C_IRQ_EXP_MASK); in HAL_IRQ_MaskAll()
764 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
771 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, 0); in HAL_IRQ_MaskAll()
780 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, _u32IRQExp_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/manhattan/irq/
H A DregIRQ.h212 #define REG_C_IRQ_EXP_MASK REG_FRC_C_IRQ_EXP_MASK macro
233 #define REG_C_IRQ_EXP_MASK REG_AEON_C_IRQ_EXP_MASK macro
258 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
284 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
308 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
331 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
355 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
H A DhalIRQ.c636 reg = REG_C_IRQ_EXP_MASK; in _HAL_IRQ_Enable()
756 _u32IRQExp_Msk = _IRQ_Read4Byte(REG_C_IRQ_EXP_MASK); in HAL_IRQ_MaskAll()
760 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
767 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, 0); in HAL_IRQ_MaskAll()
776 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, _u32IRQExp_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/maxim/irq/
H A DregIRQ.h212 #define REG_C_IRQ_EXP_MASK REG_FRC_C_IRQ_EXP_MASK macro
233 #define REG_C_IRQ_EXP_MASK REG_AEON_C_IRQ_EXP_MASK macro
258 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
284 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
308 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
331 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
355 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
H A DhalIRQ.c640 reg = REG_C_IRQ_EXP_MASK; in _HAL_IRQ_Enable()
760 _u32IRQExp_Msk = _IRQ_Read4Byte(REG_C_IRQ_EXP_MASK); in HAL_IRQ_MaskAll()
764 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
771 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, 0); in HAL_IRQ_MaskAll()
780 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, _u32IRQExp_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/M7621/irq/
H A DregIRQ.h212 #define REG_C_IRQ_EXP_MASK REG_FRC_C_IRQ_EXP_MASK macro
233 #define REG_C_IRQ_EXP_MASK REG_AEON_C_IRQ_EXP_MASK macro
258 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
284 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
308 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
331 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
355 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
H A DhalIRQ.c640 reg = REG_C_IRQ_EXP_MASK; in _HAL_IRQ_Enable()
760 _u32IRQExp_Msk = _IRQ_Read4Byte(REG_C_IRQ_EXP_MASK); in HAL_IRQ_MaskAll()
764 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
771 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, 0); in HAL_IRQ_MaskAll()
780 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, _u32IRQExp_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/mustang/irq/
H A DregIRQ.h162 #define REG_C_IRQ_EXP_MASK REG_AEON_C_IRQ_EXP_MASK macro
179 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
197 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
213 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
229 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
H A DhalIRQ.c439 reg = REG_C_IRQ_EXP_MASK; in _HAL_IRQ_Enable()
543 _u32IRQExp_Msk = _IRQ_Read4Byte(REG_C_IRQ_EXP_MASK); in HAL_IRQ_MaskAll()
547 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
554 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, 0); in HAL_IRQ_MaskAll()
563 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, _u32IRQExp_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/maldives/irq/
H A DregIRQ.h162 #define REG_C_IRQ_EXP_MASK REG_AEON_C_IRQ_EXP_MASK macro
179 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
197 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
213 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
229 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
H A DhalIRQ.c439 reg = REG_C_IRQ_EXP_MASK; in _HAL_IRQ_Enable()
543 _u32IRQExp_Msk = _IRQ_Read4Byte(REG_C_IRQ_EXP_MASK); in HAL_IRQ_MaskAll()
547 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
554 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, 0); in HAL_IRQ_MaskAll()
563 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, _u32IRQExp_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/mainz/irq/
H A DhalIRQ.c438 reg = REG_C_IRQ_EXP_MASK; in _HAL_IRQ_Enable()
547 _u32IRQExp_Msk = _IRQ_Read4Byte(REG_C_IRQ_EXP_MASK); in HAL_IRQ_MaskAll()
551 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
558 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, 0); in HAL_IRQ_MaskAll()
567 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, _u32IRQExp_Msk); in HAL_IRQ_Restore()
H A DregIRQ.h153 #define REG_C_IRQ_EXP_MASK REG_AEON_C_IRQ_EXP_MASK macro
169 #define REG_C_IRQ_EXP_MASK REG_MIPS_C_IRQ_EXP_MASK macro
/utopia/UTPA2-700.0.x/modules/irq/hal/messi/irq/
H A DhalIRQ.c438 reg = REG_C_IRQ_EXP_MASK; in _HAL_IRQ_Enable()
547 _u32IRQExp_Msk = _IRQ_Read4Byte(REG_C_IRQ_EXP_MASK); in HAL_IRQ_MaskAll()
551 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
558 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, 0); in HAL_IRQ_MaskAll()
567 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, _u32IRQExp_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/mooney/irq/
H A DhalIRQ.c438 reg = REG_C_IRQ_EXP_MASK; in _HAL_IRQ_Enable()
547 _u32IRQExp_Msk = _IRQ_Read4Byte(REG_C_IRQ_EXP_MASK); in HAL_IRQ_MaskAll()
551 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
558 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, 0); in HAL_IRQ_MaskAll()
567 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, _u32IRQExp_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/k6/irq/
H A DhalIRQ.c580 reg = REG_C_IRQ_EXP_MASK; in _HAL_IRQ_Enable()
700 _u32IRQExp_Msk = _IRQ_Read4Byte(REG_C_IRQ_EXP_MASK); in HAL_IRQ_MaskAll()
704 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
711 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, 0); in HAL_IRQ_MaskAll()
720 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, _u32IRQExp_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/k6lite/irq/
H A DhalIRQ.c580 reg = REG_C_IRQ_EXP_MASK; in _HAL_IRQ_Enable()
700 _u32IRQExp_Msk = _IRQ_Read4Byte(REG_C_IRQ_EXP_MASK); in HAL_IRQ_MaskAll()
704 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
711 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, 0); in HAL_IRQ_MaskAll()
720 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, _u32IRQExp_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/kano/irq/
H A DhalIRQ.c580 reg = REG_C_IRQ_EXP_MASK; in _HAL_IRQ_Enable()
700 _u32IRQExp_Msk = _IRQ_Read4Byte(REG_C_IRQ_EXP_MASK); in HAL_IRQ_MaskAll()
704 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
711 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, 0); in HAL_IRQ_MaskAll()
720 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, _u32IRQExp_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/k7u/irq/
H A DhalIRQ.c580 reg = REG_C_IRQ_EXP_MASK; in _HAL_IRQ_Enable()
700 _u32IRQExp_Msk = _IRQ_Read4Byte(REG_C_IRQ_EXP_MASK); in HAL_IRQ_MaskAll()
704 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
711 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, 0); in HAL_IRQ_MaskAll()
720 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, _u32IRQExp_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/curry/irq/
H A DhalIRQ.c580 reg = REG_C_IRQ_EXP_MASK; in _HAL_IRQ_Enable()
700 _u32IRQExp_Msk = _IRQ_Read4Byte(REG_C_IRQ_EXP_MASK); in HAL_IRQ_MaskAll()
704 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
711 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, 0); in HAL_IRQ_MaskAll()
720 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, _u32IRQExp_Msk); in HAL_IRQ_Restore()

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