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Searched refs:REG_C_FIQ_MASK (Results 1 – 25 of 32) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/irq/hal/M7821/irq/
H A DregIRQ.h197 #define REG_C_FIQ_MASK REG_FRC_C_FIQ_MASK macro
218 #define REG_C_FIQ_MASK REG_AEON_C_FIQ_MASK macro
243 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
269 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
293 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
316 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
340 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
363 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
H A DhalIRQ.c630 reg = REG_C_FIQ_MASK; in _HAL_IRQ_Enable()
759 _u32FIQ_Msk = _IRQ_Read4Byte(REG_C_FIQ_MASK); in HAL_IRQ_MaskAll()
763 _IRQ_Write4Byte(REG_C_FIQ_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
770 _IRQ_Write4Byte(REG_C_FIQ_MASK, 0); in HAL_IRQ_MaskAll()
779 _IRQ_Write4Byte(REG_C_FIQ_MASK, _u32FIQ_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/macan/irq/
H A DregIRQ.h197 #define REG_C_FIQ_MASK REG_FRC_C_FIQ_MASK macro
218 #define REG_C_FIQ_MASK REG_AEON_C_FIQ_MASK macro
243 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
269 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
293 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
316 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
340 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
363 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
H A DhalIRQ.c624 reg = REG_C_FIQ_MASK; in _HAL_IRQ_Enable()
752 _u32FIQ_Msk = _IRQ_Read4Byte(REG_C_FIQ_MASK); in HAL_IRQ_MaskAll()
756 _IRQ_Write4Byte(REG_C_FIQ_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
763 _IRQ_Write4Byte(REG_C_FIQ_MASK, 0); in HAL_IRQ_MaskAll()
772 _IRQ_Write4Byte(REG_C_FIQ_MASK, _u32FIQ_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/maserati/irq/
H A DregIRQ.h197 #define REG_C_FIQ_MASK REG_FRC_C_FIQ_MASK macro
218 #define REG_C_FIQ_MASK REG_AEON_C_FIQ_MASK macro
243 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
269 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
293 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
316 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
340 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
H A DhalIRQ.c628 reg = REG_C_FIQ_MASK; in _HAL_IRQ_Enable()
757 _u32FIQ_Msk = _IRQ_Read4Byte(REG_C_FIQ_MASK); in HAL_IRQ_MaskAll()
761 _IRQ_Write4Byte(REG_C_FIQ_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
768 _IRQ_Write4Byte(REG_C_FIQ_MASK, 0); in HAL_IRQ_MaskAll()
777 _IRQ_Write4Byte(REG_C_FIQ_MASK, _u32FIQ_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/manhattan/irq/
H A DregIRQ.h197 #define REG_C_FIQ_MASK REG_FRC_C_FIQ_MASK macro
218 #define REG_C_FIQ_MASK REG_AEON_C_FIQ_MASK macro
243 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
269 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
293 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
316 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
340 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
H A DhalIRQ.c624 reg = REG_C_FIQ_MASK; in _HAL_IRQ_Enable()
753 _u32FIQ_Msk = _IRQ_Read4Byte(REG_C_FIQ_MASK); in HAL_IRQ_MaskAll()
757 _IRQ_Write4Byte(REG_C_FIQ_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
764 _IRQ_Write4Byte(REG_C_FIQ_MASK, 0); in HAL_IRQ_MaskAll()
773 _IRQ_Write4Byte(REG_C_FIQ_MASK, _u32FIQ_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/maxim/irq/
H A DregIRQ.h197 #define REG_C_FIQ_MASK REG_FRC_C_FIQ_MASK macro
218 #define REG_C_FIQ_MASK REG_AEON_C_FIQ_MASK macro
243 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
269 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
293 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
316 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
340 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
H A DhalIRQ.c628 reg = REG_C_FIQ_MASK; in _HAL_IRQ_Enable()
757 _u32FIQ_Msk = _IRQ_Read4Byte(REG_C_FIQ_MASK); in HAL_IRQ_MaskAll()
761 _IRQ_Write4Byte(REG_C_FIQ_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
768 _IRQ_Write4Byte(REG_C_FIQ_MASK, 0); in HAL_IRQ_MaskAll()
777 _IRQ_Write4Byte(REG_C_FIQ_MASK, _u32FIQ_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/M7621/irq/
H A DregIRQ.h197 #define REG_C_FIQ_MASK REG_FRC_C_FIQ_MASK macro
218 #define REG_C_FIQ_MASK REG_AEON_C_FIQ_MASK macro
243 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
269 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
293 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
316 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
340 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
H A DhalIRQ.c628 reg = REG_C_FIQ_MASK; in _HAL_IRQ_Enable()
757 _u32FIQ_Msk = _IRQ_Read4Byte(REG_C_FIQ_MASK); in HAL_IRQ_MaskAll()
761 _IRQ_Write4Byte(REG_C_FIQ_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
768 _IRQ_Write4Byte(REG_C_FIQ_MASK, 0); in HAL_IRQ_MaskAll()
777 _IRQ_Write4Byte(REG_C_FIQ_MASK, _u32FIQ_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/mustang/irq/
H A DregIRQ.h151 #define REG_C_FIQ_MASK REG_AEON_C_FIQ_MASK macro
168 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
186 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
202 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
218 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
H A DhalIRQ.c434 reg = REG_C_FIQ_MASK; in _HAL_IRQ_Enable()
540 _u32FIQ_Msk = _IRQ_Read4Byte(REG_C_FIQ_MASK); in HAL_IRQ_MaskAll()
544 _IRQ_Write4Byte(REG_C_FIQ_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
551 _IRQ_Write4Byte(REG_C_FIQ_MASK, 0); in HAL_IRQ_MaskAll()
560 _IRQ_Write4Byte(REG_C_FIQ_MASK, _u32FIQ_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/maldives/irq/
H A DregIRQ.h151 #define REG_C_FIQ_MASK REG_AEON_C_FIQ_MASK macro
168 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
186 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
202 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
218 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
H A DhalIRQ.c434 reg = REG_C_FIQ_MASK; in _HAL_IRQ_Enable()
540 _u32FIQ_Msk = _IRQ_Read4Byte(REG_C_FIQ_MASK); in HAL_IRQ_MaskAll()
544 _IRQ_Write4Byte(REG_C_FIQ_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
551 _IRQ_Write4Byte(REG_C_FIQ_MASK, 0); in HAL_IRQ_MaskAll()
560 _IRQ_Write4Byte(REG_C_FIQ_MASK, _u32FIQ_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/mainz/irq/
H A DhalIRQ.c433 reg = REG_C_FIQ_MASK; in _HAL_IRQ_Enable()
544 _u32FIQ_Msk = _IRQ_Read4Byte(REG_C_FIQ_MASK); in HAL_IRQ_MaskAll()
548 _IRQ_Write4Byte(REG_C_FIQ_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
555 _IRQ_Write4Byte(REG_C_FIQ_MASK, 0); in HAL_IRQ_MaskAll()
564 _IRQ_Write4Byte(REG_C_FIQ_MASK, _u32FIQ_Msk); in HAL_IRQ_Restore()
H A DregIRQ.h142 #define REG_C_FIQ_MASK REG_AEON_C_FIQ_MASK macro
158 #define REG_C_FIQ_MASK REG_MIPS_C_FIQ_MASK macro
/utopia/UTPA2-700.0.x/modules/irq/hal/messi/irq/
H A DhalIRQ.c433 reg = REG_C_FIQ_MASK; in _HAL_IRQ_Enable()
544 _u32FIQ_Msk = _IRQ_Read4Byte(REG_C_FIQ_MASK); in HAL_IRQ_MaskAll()
548 _IRQ_Write4Byte(REG_C_FIQ_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
555 _IRQ_Write4Byte(REG_C_FIQ_MASK, 0); in HAL_IRQ_MaskAll()
564 _IRQ_Write4Byte(REG_C_FIQ_MASK, _u32FIQ_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/mooney/irq/
H A DhalIRQ.c433 reg = REG_C_FIQ_MASK; in _HAL_IRQ_Enable()
544 _u32FIQ_Msk = _IRQ_Read4Byte(REG_C_FIQ_MASK); in HAL_IRQ_MaskAll()
548 _IRQ_Write4Byte(REG_C_FIQ_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
555 _IRQ_Write4Byte(REG_C_FIQ_MASK, 0); in HAL_IRQ_MaskAll()
564 _IRQ_Write4Byte(REG_C_FIQ_MASK, _u32FIQ_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/k6/irq/
H A DhalIRQ.c575 reg = REG_C_FIQ_MASK; in _HAL_IRQ_Enable()
697 _u32FIQ_Msk = _IRQ_Read4Byte(REG_C_FIQ_MASK); in HAL_IRQ_MaskAll()
701 _IRQ_Write4Byte(REG_C_FIQ_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
708 _IRQ_Write4Byte(REG_C_FIQ_MASK, 0); in HAL_IRQ_MaskAll()
717 _IRQ_Write4Byte(REG_C_FIQ_MASK, _u32FIQ_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/k6lite/irq/
H A DhalIRQ.c575 reg = REG_C_FIQ_MASK; in _HAL_IRQ_Enable()
697 _u32FIQ_Msk = _IRQ_Read4Byte(REG_C_FIQ_MASK); in HAL_IRQ_MaskAll()
701 _IRQ_Write4Byte(REG_C_FIQ_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
708 _IRQ_Write4Byte(REG_C_FIQ_MASK, 0); in HAL_IRQ_MaskAll()
717 _IRQ_Write4Byte(REG_C_FIQ_MASK, _u32FIQ_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/kano/irq/
H A DhalIRQ.c575 reg = REG_C_FIQ_MASK; in _HAL_IRQ_Enable()
697 _u32FIQ_Msk = _IRQ_Read4Byte(REG_C_FIQ_MASK); in HAL_IRQ_MaskAll()
701 _IRQ_Write4Byte(REG_C_FIQ_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
708 _IRQ_Write4Byte(REG_C_FIQ_MASK, 0); in HAL_IRQ_MaskAll()
717 _IRQ_Write4Byte(REG_C_FIQ_MASK, _u32FIQ_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/k7u/irq/
H A DhalIRQ.c575 reg = REG_C_FIQ_MASK; in _HAL_IRQ_Enable()
697 _u32FIQ_Msk = _IRQ_Read4Byte(REG_C_FIQ_MASK); in HAL_IRQ_MaskAll()
701 _IRQ_Write4Byte(REG_C_FIQ_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
708 _IRQ_Write4Byte(REG_C_FIQ_MASK, 0); in HAL_IRQ_MaskAll()
717 _IRQ_Write4Byte(REG_C_FIQ_MASK, _u32FIQ_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/curry/irq/
H A DhalIRQ.c575 reg = REG_C_FIQ_MASK; in _HAL_IRQ_Enable()
697 _u32FIQ_Msk = _IRQ_Read4Byte(REG_C_FIQ_MASK); in HAL_IRQ_MaskAll()
701 _IRQ_Write4Byte(REG_C_FIQ_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
708 _IRQ_Write4Byte(REG_C_FIQ_MASK, 0); in HAL_IRQ_MaskAll()
717 _IRQ_Write4Byte(REG_C_FIQ_MASK, _u32FIQ_Msk); in HAL_IRQ_Restore()

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