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Searched refs:REG_C_FIQ_EXP_MASK (Results 1 – 25 of 32) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/irq/hal/M7821/irq/
H A DregIRQ.h204 #define REG_C_FIQ_EXP_MASK REG_FRC_C_FIQ_EXP_MASK macro
225 #define REG_C_FIQ_EXP_MASK REG_AEON_C_FIQ_EXP_MASK macro
250 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
276 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
300 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
323 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
347 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
370 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
H A DhalIRQ.c647 reg = REG_C_FIQ_EXP_MASK; in _HAL_IRQ_Enable()
761 _u32FIQExp_Msk = _IRQ_Read4Byte(REG_C_FIQ_EXP_MASK); in HAL_IRQ_MaskAll()
765 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
772 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, 0); in HAL_IRQ_MaskAll()
781 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, _u32FIQExp_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/macan/irq/
H A DregIRQ.h204 #define REG_C_FIQ_EXP_MASK REG_FRC_C_FIQ_EXP_MASK macro
225 #define REG_C_FIQ_EXP_MASK REG_AEON_C_FIQ_EXP_MASK macro
250 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
276 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
300 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
323 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
347 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
370 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
H A DhalIRQ.c641 reg = REG_C_FIQ_EXP_MASK; in _HAL_IRQ_Enable()
754 _u32FIQExp_Msk = _IRQ_Read4Byte(REG_C_FIQ_EXP_MASK); in HAL_IRQ_MaskAll()
758 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
765 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, 0); in HAL_IRQ_MaskAll()
774 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, _u32FIQExp_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/maserati/irq/
H A DregIRQ.h204 #define REG_C_FIQ_EXP_MASK REG_FRC_C_FIQ_EXP_MASK macro
225 #define REG_C_FIQ_EXP_MASK REG_AEON_C_FIQ_EXP_MASK macro
250 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
276 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
300 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
323 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
347 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
H A DhalIRQ.c645 reg = REG_C_FIQ_EXP_MASK; in _HAL_IRQ_Enable()
759 _u32FIQExp_Msk = _IRQ_Read4Byte(REG_C_FIQ_EXP_MASK); in HAL_IRQ_MaskAll()
763 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
770 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, 0); in HAL_IRQ_MaskAll()
779 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, _u32FIQExp_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/manhattan/irq/
H A DregIRQ.h204 #define REG_C_FIQ_EXP_MASK REG_FRC_C_FIQ_EXP_MASK macro
225 #define REG_C_FIQ_EXP_MASK REG_AEON_C_FIQ_EXP_MASK macro
250 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
276 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
300 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
323 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
347 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
H A DhalIRQ.c641 reg = REG_C_FIQ_EXP_MASK; in _HAL_IRQ_Enable()
755 _u32FIQExp_Msk = _IRQ_Read4Byte(REG_C_FIQ_EXP_MASK); in HAL_IRQ_MaskAll()
759 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
766 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, 0); in HAL_IRQ_MaskAll()
775 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, _u32FIQExp_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/maxim/irq/
H A DregIRQ.h204 #define REG_C_FIQ_EXP_MASK REG_FRC_C_FIQ_EXP_MASK macro
225 #define REG_C_FIQ_EXP_MASK REG_AEON_C_FIQ_EXP_MASK macro
250 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
276 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
300 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
323 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
347 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
H A DhalIRQ.c645 reg = REG_C_FIQ_EXP_MASK; in _HAL_IRQ_Enable()
759 _u32FIQExp_Msk = _IRQ_Read4Byte(REG_C_FIQ_EXP_MASK); in HAL_IRQ_MaskAll()
763 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
770 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, 0); in HAL_IRQ_MaskAll()
779 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, _u32FIQExp_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/M7621/irq/
H A DregIRQ.h204 #define REG_C_FIQ_EXP_MASK REG_FRC_C_FIQ_EXP_MASK macro
225 #define REG_C_FIQ_EXP_MASK REG_AEON_C_FIQ_EXP_MASK macro
250 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
276 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
300 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
323 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
347 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
H A DhalIRQ.c645 reg = REG_C_FIQ_EXP_MASK; in _HAL_IRQ_Enable()
759 _u32FIQExp_Msk = _IRQ_Read4Byte(REG_C_FIQ_EXP_MASK); in HAL_IRQ_MaskAll()
763 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
770 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, 0); in HAL_IRQ_MaskAll()
779 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, _u32FIQExp_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/mustang/irq/
H A DregIRQ.h158 #define REG_C_FIQ_EXP_MASK REG_AEON_C_FIQ_EXP_MASK macro
175 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
193 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
209 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
225 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
H A DhalIRQ.c444 reg = REG_C_FIQ_EXP_MASK; in _HAL_IRQ_Enable()
542 _u32FIQExp_Msk = _IRQ_Read4Byte(REG_C_FIQ_EXP_MASK); in HAL_IRQ_MaskAll()
546 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
553 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, 0); in HAL_IRQ_MaskAll()
562 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, _u32FIQExp_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/maldives/irq/
H A DregIRQ.h158 #define REG_C_FIQ_EXP_MASK REG_AEON_C_FIQ_EXP_MASK macro
175 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
193 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
209 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
225 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
H A DhalIRQ.c444 reg = REG_C_FIQ_EXP_MASK; in _HAL_IRQ_Enable()
542 _u32FIQExp_Msk = _IRQ_Read4Byte(REG_C_FIQ_EXP_MASK); in HAL_IRQ_MaskAll()
546 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
553 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, 0); in HAL_IRQ_MaskAll()
562 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, _u32FIQExp_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/mainz/irq/
H A DhalIRQ.c443 reg = REG_C_FIQ_EXP_MASK; in _HAL_IRQ_Enable()
546 _u32FIQExp_Msk = _IRQ_Read4Byte(REG_C_FIQ_EXP_MASK); in HAL_IRQ_MaskAll()
550 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
557 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, 0); in HAL_IRQ_MaskAll()
566 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, _u32FIQExp_Msk); in HAL_IRQ_Restore()
H A DregIRQ.h149 #define REG_C_FIQ_EXP_MASK REG_AEON_C_FIQ_EXP_MASK macro
165 #define REG_C_FIQ_EXP_MASK REG_MIPS_C_FIQ_EXP_MASK macro
/utopia/UTPA2-700.0.x/modules/irq/hal/messi/irq/
H A DhalIRQ.c443 reg = REG_C_FIQ_EXP_MASK; in _HAL_IRQ_Enable()
546 _u32FIQExp_Msk = _IRQ_Read4Byte(REG_C_FIQ_EXP_MASK); in HAL_IRQ_MaskAll()
550 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
557 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, 0); in HAL_IRQ_MaskAll()
566 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, _u32FIQExp_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/mooney/irq/
H A DhalIRQ.c443 reg = REG_C_FIQ_EXP_MASK; in _HAL_IRQ_Enable()
546 _u32FIQExp_Msk = _IRQ_Read4Byte(REG_C_FIQ_EXP_MASK); in HAL_IRQ_MaskAll()
550 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
557 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, 0); in HAL_IRQ_MaskAll()
566 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, _u32FIQExp_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/k6/irq/
H A DhalIRQ.c585 reg = REG_C_FIQ_EXP_MASK; in _HAL_IRQ_Enable()
699 _u32FIQExp_Msk = _IRQ_Read4Byte(REG_C_FIQ_EXP_MASK); in HAL_IRQ_MaskAll()
703 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
710 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, 0); in HAL_IRQ_MaskAll()
719 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, _u32FIQExp_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/k6lite/irq/
H A DhalIRQ.c585 reg = REG_C_FIQ_EXP_MASK; in _HAL_IRQ_Enable()
699 _u32FIQExp_Msk = _IRQ_Read4Byte(REG_C_FIQ_EXP_MASK); in HAL_IRQ_MaskAll()
703 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
710 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, 0); in HAL_IRQ_MaskAll()
719 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, _u32FIQExp_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/kano/irq/
H A DhalIRQ.c585 reg = REG_C_FIQ_EXP_MASK; in _HAL_IRQ_Enable()
699 _u32FIQExp_Msk = _IRQ_Read4Byte(REG_C_FIQ_EXP_MASK); in HAL_IRQ_MaskAll()
703 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
710 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, 0); in HAL_IRQ_MaskAll()
719 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, _u32FIQExp_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/k7u/irq/
H A DhalIRQ.c585 reg = REG_C_FIQ_EXP_MASK; in _HAL_IRQ_Enable()
699 _u32FIQExp_Msk = _IRQ_Read4Byte(REG_C_FIQ_EXP_MASK); in HAL_IRQ_MaskAll()
703 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
710 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, 0); in HAL_IRQ_MaskAll()
719 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, _u32FIQExp_Msk); in HAL_IRQ_Restore()
/utopia/UTPA2-700.0.x/modules/irq/hal/curry/irq/
H A DhalIRQ.c585 reg = REG_C_FIQ_EXP_MASK; in _HAL_IRQ_Enable()
699 _u32FIQExp_Msk = _IRQ_Read4Byte(REG_C_FIQ_EXP_MASK); in HAL_IRQ_MaskAll()
703 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, 0xFFFFFFFF); in HAL_IRQ_MaskAll()
710 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, 0); in HAL_IRQ_MaskAll()
719 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, _u32FIQExp_Msk); in HAL_IRQ_Restore()

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