Home
last modified time | relevance | path

Searched refs:REG_CPU_INT_BASE (Results 1 – 15 of 15) sorted by relevance

/utopia/UTPA2-700.0.x/modules/mbx/hal/mainz/mbx/
H A DregMBXINT.h133 #define REG_CPU_INT_BASE (0x2A0<<1) macro
134 #define CPU_INT_REG(address) RIU[address*2+REG_CPU_INT_BASE]
/utopia/UTPA2-700.0.x/modules/mbx/hal/maldives/mbx/
H A DregMBXINT.h136 #define REG_CPU_INT_BASE (0x2A0<<1) macro
137 #define CPU_INT_REG(address) RIU[address*2+REG_CPU_INT_BASE]
/utopia/UTPA2-700.0.x/modules/mbx/hal/k6/mbx/
H A DregMBXINT.h146 #define REG_CPU_INT_BASE (0x2A0<<1) macro
147 #define CPU_INT_REG(address) RIU[address*2+REG_CPU_INT_BASE]
/utopia/UTPA2-700.0.x/modules/mbx/hal/mooney/mbx/
H A DregMBXINT.h133 #define REG_CPU_INT_BASE (0x2A0<<1) macro
134 #define CPU_INT_REG(address) RIU[address*2+REG_CPU_INT_BASE]
/utopia/UTPA2-700.0.x/modules/mbx/hal/kano/mbx/
H A DregMBXINT.h146 #define REG_CPU_INT_BASE (0x2A0<<1) macro
147 #define CPU_INT_REG(address) RIU[address*2+REG_CPU_INT_BASE]
/utopia/UTPA2-700.0.x/modules/mbx/hal/mustang/mbx/
H A DregMBXINT.h136 #define REG_CPU_INT_BASE (0x2A0<<1) macro
137 #define CPU_INT_REG(address) RIU[address*2+REG_CPU_INT_BASE]
/utopia/UTPA2-700.0.x/modules/mbx/hal/messi/mbx/
H A DregMBXINT.h133 #define REG_CPU_INT_BASE (0x2A0<<1) macro
134 #define CPU_INT_REG(address) RIU[address*2+REG_CPU_INT_BASE]
/utopia/UTPA2-700.0.x/modules/mbx/hal/k6lite/mbx/
H A DregMBXINT.h146 #define REG_CPU_INT_BASE (0x2A0<<1) macro
147 #define CPU_INT_REG(address) RIU[address*2+REG_CPU_INT_BASE]
/utopia/UTPA2-700.0.x/modules/mbx/hal/curry/mbx/
H A DregMBXINT.h146 #define REG_CPU_INT_BASE (0x2A0<<1) macro
147 #define CPU_INT_REG(address) RIU[address*2+REG_CPU_INT_BASE]
/utopia/UTPA2-700.0.x/modules/mbx/hal/manhattan/mbx/
H A DregMBXINT.h158 #define REG_CPU_INT_BASE (0x2A0<<1)//(0x100540-0x100000) macro
159 #define CPU_INT_REG(address) RIU[address*2+REG_CPU_INT_BASE]
/utopia/UTPA2-700.0.x/modules/mbx/hal/macan/mbx/
H A DregMBXINT.h158 #define REG_CPU_INT_BASE (0x2A0<<1)//(0x100540-0x100000) macro
159 #define CPU_INT_REG(address) RIU[address*2+REG_CPU_INT_BASE]
/utopia/UTPA2-700.0.x/modules/mbx/hal/M7621/mbx/
H A DregMBXINT.h160 #define REG_CPU_INT_BASE (0x2A0<<1)//(0x100540-0x100000) macro
161 #define CPU_INT_REG(address) RIU[address*2+REG_CPU_INT_BASE]
/utopia/UTPA2-700.0.x/modules/mbx/hal/maserati/mbx/
H A DregMBXINT.h158 #define REG_CPU_INT_BASE (0x2A0<<1)//(0x100540-0x100000) macro
159 #define CPU_INT_REG(address) RIU[address*2+REG_CPU_INT_BASE]
/utopia/UTPA2-700.0.x/modules/mbx/hal/maxim/mbx/
H A DregMBXINT.h158 #define REG_CPU_INT_BASE (0x2A0<<1)//(0x100540-0x100000) macro
159 #define CPU_INT_REG(address) RIU[address*2+REG_CPU_INT_BASE]
/utopia/UTPA2-700.0.x/modules/mbx/hal/M7821/mbx/
H A DregMBXINT.h160 #define REG_CPU_INT_BASE (0x2A0<<1)//(0x100540-0x100000) macro
161 #define CPU_INT_REG(address) RIU[address*2+REG_CPU_INT_BASE]