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Searched refs:REG_COMBO_PHY1_P3_BASE (Results 1 – 25 of 27) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h3303 #define REG_COMBO_PHY1_P3_00_L (REG_COMBO_PHY1_P3_BASE + 0x00)
3304 #define REG_COMBO_PHY1_P3_00_H (REG_COMBO_PHY1_P3_BASE + 0x01)
3305 #define REG_COMBO_PHY1_P3_01_L (REG_COMBO_PHY1_P3_BASE + 0x02)
3306 #define REG_COMBO_PHY1_P3_01_H (REG_COMBO_PHY1_P3_BASE + 0x03)
3307 #define REG_COMBO_PHY1_P3_02_L (REG_COMBO_PHY1_P3_BASE + 0x04)
3308 #define REG_COMBO_PHY1_P3_02_H (REG_COMBO_PHY1_P3_BASE + 0x05)
3309 #define REG_COMBO_PHY1_P3_03_L (REG_COMBO_PHY1_P3_BASE + 0x06)
3310 #define REG_COMBO_PHY1_P3_03_H (REG_COMBO_PHY1_P3_BASE + 0x07)
3311 #define REG_COMBO_PHY1_P3_04_L (REG_COMBO_PHY1_P3_BASE + 0x08)
3312 #define REG_COMBO_PHY1_P3_04_H (REG_COMBO_PHY1_P3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h586 #define REG_COMBO_PHY1_P3_BASE 0x170900UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h3305 #define REG_COMBO_PHY1_P3_00_L (REG_COMBO_PHY1_P3_BASE + 0x00)
3306 #define REG_COMBO_PHY1_P3_00_H (REG_COMBO_PHY1_P3_BASE + 0x01)
3307 #define REG_COMBO_PHY1_P3_01_L (REG_COMBO_PHY1_P3_BASE + 0x02)
3308 #define REG_COMBO_PHY1_P3_01_H (REG_COMBO_PHY1_P3_BASE + 0x03)
3309 #define REG_COMBO_PHY1_P3_02_L (REG_COMBO_PHY1_P3_BASE + 0x04)
3310 #define REG_COMBO_PHY1_P3_02_H (REG_COMBO_PHY1_P3_BASE + 0x05)
3311 #define REG_COMBO_PHY1_P3_03_L (REG_COMBO_PHY1_P3_BASE + 0x06)
3312 #define REG_COMBO_PHY1_P3_03_H (REG_COMBO_PHY1_P3_BASE + 0x07)
3313 #define REG_COMBO_PHY1_P3_04_L (REG_COMBO_PHY1_P3_BASE + 0x08)
3314 #define REG_COMBO_PHY1_P3_04_H (REG_COMBO_PHY1_P3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h568 #define REG_COMBO_PHY1_P3_BASE REG_COMBO_PHY1_P0_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h3303 #define REG_COMBO_PHY1_P3_00_L (REG_COMBO_PHY1_P3_BASE + 0x00)
3304 #define REG_COMBO_PHY1_P3_00_H (REG_COMBO_PHY1_P3_BASE + 0x01)
3305 #define REG_COMBO_PHY1_P3_01_L (REG_COMBO_PHY1_P3_BASE + 0x02)
3306 #define REG_COMBO_PHY1_P3_01_H (REG_COMBO_PHY1_P3_BASE + 0x03)
3307 #define REG_COMBO_PHY1_P3_02_L (REG_COMBO_PHY1_P3_BASE + 0x04)
3308 #define REG_COMBO_PHY1_P3_02_H (REG_COMBO_PHY1_P3_BASE + 0x05)
3309 #define REG_COMBO_PHY1_P3_03_L (REG_COMBO_PHY1_P3_BASE + 0x06)
3310 #define REG_COMBO_PHY1_P3_03_H (REG_COMBO_PHY1_P3_BASE + 0x07)
3311 #define REG_COMBO_PHY1_P3_04_L (REG_COMBO_PHY1_P3_BASE + 0x08)
3312 #define REG_COMBO_PHY1_P3_04_H (REG_COMBO_PHY1_P3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h546 #define REG_COMBO_PHY1_P3_BASE 0x170900UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h3305 #define REG_COMBO_PHY1_P3_00_L (REG_COMBO_PHY1_P3_BASE + 0x00)
3306 #define REG_COMBO_PHY1_P3_00_H (REG_COMBO_PHY1_P3_BASE + 0x01)
3307 #define REG_COMBO_PHY1_P3_01_L (REG_COMBO_PHY1_P3_BASE + 0x02)
3308 #define REG_COMBO_PHY1_P3_01_H (REG_COMBO_PHY1_P3_BASE + 0x03)
3309 #define REG_COMBO_PHY1_P3_02_L (REG_COMBO_PHY1_P3_BASE + 0x04)
3310 #define REG_COMBO_PHY1_P3_02_H (REG_COMBO_PHY1_P3_BASE + 0x05)
3311 #define REG_COMBO_PHY1_P3_03_L (REG_COMBO_PHY1_P3_BASE + 0x06)
3312 #define REG_COMBO_PHY1_P3_03_H (REG_COMBO_PHY1_P3_BASE + 0x07)
3313 #define REG_COMBO_PHY1_P3_04_L (REG_COMBO_PHY1_P3_BASE + 0x08)
3314 #define REG_COMBO_PHY1_P3_04_H (REG_COMBO_PHY1_P3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h570 #define REG_COMBO_PHY1_P3_BASE REG_COMBO_PHY1_P0_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h3303 #define REG_COMBO_PHY1_P3_00_L (REG_COMBO_PHY1_P3_BASE + 0x00)
3304 #define REG_COMBO_PHY1_P3_00_H (REG_COMBO_PHY1_P3_BASE + 0x01)
3305 #define REG_COMBO_PHY1_P3_01_L (REG_COMBO_PHY1_P3_BASE + 0x02)
3306 #define REG_COMBO_PHY1_P3_01_H (REG_COMBO_PHY1_P3_BASE + 0x03)
3307 #define REG_COMBO_PHY1_P3_02_L (REG_COMBO_PHY1_P3_BASE + 0x04)
3308 #define REG_COMBO_PHY1_P3_02_H (REG_COMBO_PHY1_P3_BASE + 0x05)
3309 #define REG_COMBO_PHY1_P3_03_L (REG_COMBO_PHY1_P3_BASE + 0x06)
3310 #define REG_COMBO_PHY1_P3_03_H (REG_COMBO_PHY1_P3_BASE + 0x07)
3311 #define REG_COMBO_PHY1_P3_04_L (REG_COMBO_PHY1_P3_BASE + 0x08)
3312 #define REG_COMBO_PHY1_P3_04_H (REG_COMBO_PHY1_P3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h573 #define REG_COMBO_PHY1_P3_BASE 0x170900UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h3305 #define REG_COMBO_PHY1_P3_00_L (REG_COMBO_PHY1_P3_BASE + 0x00)
3306 #define REG_COMBO_PHY1_P3_00_H (REG_COMBO_PHY1_P3_BASE + 0x01)
3307 #define REG_COMBO_PHY1_P3_01_L (REG_COMBO_PHY1_P3_BASE + 0x02)
3308 #define REG_COMBO_PHY1_P3_01_H (REG_COMBO_PHY1_P3_BASE + 0x03)
3309 #define REG_COMBO_PHY1_P3_02_L (REG_COMBO_PHY1_P3_BASE + 0x04)
3310 #define REG_COMBO_PHY1_P3_02_H (REG_COMBO_PHY1_P3_BASE + 0x05)
3311 #define REG_COMBO_PHY1_P3_03_L (REG_COMBO_PHY1_P3_BASE + 0x06)
3312 #define REG_COMBO_PHY1_P3_03_H (REG_COMBO_PHY1_P3_BASE + 0x07)
3313 #define REG_COMBO_PHY1_P3_04_L (REG_COMBO_PHY1_P3_BASE + 0x08)
3314 #define REG_COMBO_PHY1_P3_04_H (REG_COMBO_PHY1_P3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h562 #define REG_COMBO_PHY1_P3_BASE REG_COMBO_PHY1_P0_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h3305 #define REG_COMBO_PHY1_P3_00_L (REG_COMBO_PHY1_P3_BASE + 0x00)
3306 #define REG_COMBO_PHY1_P3_00_H (REG_COMBO_PHY1_P3_BASE + 0x01)
3307 #define REG_COMBO_PHY1_P3_01_L (REG_COMBO_PHY1_P3_BASE + 0x02)
3308 #define REG_COMBO_PHY1_P3_01_H (REG_COMBO_PHY1_P3_BASE + 0x03)
3309 #define REG_COMBO_PHY1_P3_02_L (REG_COMBO_PHY1_P3_BASE + 0x04)
3310 #define REG_COMBO_PHY1_P3_02_H (REG_COMBO_PHY1_P3_BASE + 0x05)
3311 #define REG_COMBO_PHY1_P3_03_L (REG_COMBO_PHY1_P3_BASE + 0x06)
3312 #define REG_COMBO_PHY1_P3_03_H (REG_COMBO_PHY1_P3_BASE + 0x07)
3313 #define REG_COMBO_PHY1_P3_04_L (REG_COMBO_PHY1_P3_BASE + 0x08)
3314 #define REG_COMBO_PHY1_P3_04_H (REG_COMBO_PHY1_P3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h568 #define REG_COMBO_PHY1_P3_BASE REG_COMBO_PHY1_P0_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h3303 #define REG_COMBO_PHY1_P3_00_L (REG_COMBO_PHY1_P3_BASE + 0x00)
3304 #define REG_COMBO_PHY1_P3_00_H (REG_COMBO_PHY1_P3_BASE + 0x01)
3305 #define REG_COMBO_PHY1_P3_01_L (REG_COMBO_PHY1_P3_BASE + 0x02)
3306 #define REG_COMBO_PHY1_P3_01_H (REG_COMBO_PHY1_P3_BASE + 0x03)
3307 #define REG_COMBO_PHY1_P3_02_L (REG_COMBO_PHY1_P3_BASE + 0x04)
3308 #define REG_COMBO_PHY1_P3_02_H (REG_COMBO_PHY1_P3_BASE + 0x05)
3309 #define REG_COMBO_PHY1_P3_03_L (REG_COMBO_PHY1_P3_BASE + 0x06)
3310 #define REG_COMBO_PHY1_P3_03_H (REG_COMBO_PHY1_P3_BASE + 0x07)
3311 #define REG_COMBO_PHY1_P3_04_L (REG_COMBO_PHY1_P3_BASE + 0x08)
3312 #define REG_COMBO_PHY1_P3_04_H (REG_COMBO_PHY1_P3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h544 #define REG_COMBO_PHY1_P3_BASE 0x170900UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h3304 #define REG_COMBO_PHY1_P3_00_L (REG_COMBO_PHY1_P3_BASE + 0x00)
3305 #define REG_COMBO_PHY1_P3_00_H (REG_COMBO_PHY1_P3_BASE + 0x01)
3306 #define REG_COMBO_PHY1_P3_01_L (REG_COMBO_PHY1_P3_BASE + 0x02)
3307 #define REG_COMBO_PHY1_P3_01_H (REG_COMBO_PHY1_P3_BASE + 0x03)
3308 #define REG_COMBO_PHY1_P3_02_L (REG_COMBO_PHY1_P3_BASE + 0x04)
3309 #define REG_COMBO_PHY1_P3_02_H (REG_COMBO_PHY1_P3_BASE + 0x05)
3310 #define REG_COMBO_PHY1_P3_03_L (REG_COMBO_PHY1_P3_BASE + 0x06)
3311 #define REG_COMBO_PHY1_P3_03_H (REG_COMBO_PHY1_P3_BASE + 0x07)
3312 #define REG_COMBO_PHY1_P3_04_L (REG_COMBO_PHY1_P3_BASE + 0x08)
3313 #define REG_COMBO_PHY1_P3_04_H (REG_COMBO_PHY1_P3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h527 #define REG_COMBO_PHY1_P3_BASE 0x170900UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h3303 #define REG_COMBO_PHY1_P3_00_L (REG_COMBO_PHY1_P3_BASE + 0x00)
3304 #define REG_COMBO_PHY1_P3_00_H (REG_COMBO_PHY1_P3_BASE + 0x01)
3305 #define REG_COMBO_PHY1_P3_01_L (REG_COMBO_PHY1_P3_BASE + 0x02)
3306 #define REG_COMBO_PHY1_P3_01_H (REG_COMBO_PHY1_P3_BASE + 0x03)
3307 #define REG_COMBO_PHY1_P3_02_L (REG_COMBO_PHY1_P3_BASE + 0x04)
3308 #define REG_COMBO_PHY1_P3_02_H (REG_COMBO_PHY1_P3_BASE + 0x05)
3309 #define REG_COMBO_PHY1_P3_03_L (REG_COMBO_PHY1_P3_BASE + 0x06)
3310 #define REG_COMBO_PHY1_P3_03_H (REG_COMBO_PHY1_P3_BASE + 0x07)
3311 #define REG_COMBO_PHY1_P3_04_L (REG_COMBO_PHY1_P3_BASE + 0x08)
3312 #define REG_COMBO_PHY1_P3_04_H (REG_COMBO_PHY1_P3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h620 #define REG_COMBO_PHY1_P3_BASE 0x170900UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h3303 #define REG_COMBO_PHY1_P3_00_L (REG_COMBO_PHY1_P3_BASE + 0x00)
3304 #define REG_COMBO_PHY1_P3_00_H (REG_COMBO_PHY1_P3_BASE + 0x01)
3305 #define REG_COMBO_PHY1_P3_01_L (REG_COMBO_PHY1_P3_BASE + 0x02)
3306 #define REG_COMBO_PHY1_P3_01_H (REG_COMBO_PHY1_P3_BASE + 0x03)
3307 #define REG_COMBO_PHY1_P3_02_L (REG_COMBO_PHY1_P3_BASE + 0x04)
3308 #define REG_COMBO_PHY1_P3_02_H (REG_COMBO_PHY1_P3_BASE + 0x05)
3309 #define REG_COMBO_PHY1_P3_03_L (REG_COMBO_PHY1_P3_BASE + 0x06)
3310 #define REG_COMBO_PHY1_P3_03_H (REG_COMBO_PHY1_P3_BASE + 0x07)
3311 #define REG_COMBO_PHY1_P3_04_L (REG_COMBO_PHY1_P3_BASE + 0x08)
3312 #define REG_COMBO_PHY1_P3_04_H (REG_COMBO_PHY1_P3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h632 #define REG_COMBO_PHY1_P3_BASE 0x170900UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h3303 #define REG_COMBO_PHY1_P3_00_L (REG_COMBO_PHY1_P3_BASE + 0x00)
3304 #define REG_COMBO_PHY1_P3_00_H (REG_COMBO_PHY1_P3_BASE + 0x01)
3305 #define REG_COMBO_PHY1_P3_01_L (REG_COMBO_PHY1_P3_BASE + 0x02)
3306 #define REG_COMBO_PHY1_P3_01_H (REG_COMBO_PHY1_P3_BASE + 0x03)
3307 #define REG_COMBO_PHY1_P3_02_L (REG_COMBO_PHY1_P3_BASE + 0x04)
3308 #define REG_COMBO_PHY1_P3_02_H (REG_COMBO_PHY1_P3_BASE + 0x05)
3309 #define REG_COMBO_PHY1_P3_03_L (REG_COMBO_PHY1_P3_BASE + 0x06)
3310 #define REG_COMBO_PHY1_P3_03_H (REG_COMBO_PHY1_P3_BASE + 0x07)
3311 #define REG_COMBO_PHY1_P3_04_L (REG_COMBO_PHY1_P3_BASE + 0x08)
3312 #define REG_COMBO_PHY1_P3_04_H (REG_COMBO_PHY1_P3_BASE + 0x09)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_hdmi.h3303 #define REG_COMBO_PHY1_P3_00_L (REG_COMBO_PHY1_P3_BASE + 0x00)
3304 #define REG_COMBO_PHY1_P3_00_H (REG_COMBO_PHY1_P3_BASE + 0x01)
3305 #define REG_COMBO_PHY1_P3_01_L (REG_COMBO_PHY1_P3_BASE + 0x02)
3306 #define REG_COMBO_PHY1_P3_01_H (REG_COMBO_PHY1_P3_BASE + 0x03)
3307 #define REG_COMBO_PHY1_P3_02_L (REG_COMBO_PHY1_P3_BASE + 0x04)
3308 #define REG_COMBO_PHY1_P3_02_H (REG_COMBO_PHY1_P3_BASE + 0x05)
3309 #define REG_COMBO_PHY1_P3_03_L (REG_COMBO_PHY1_P3_BASE + 0x06)
3310 #define REG_COMBO_PHY1_P3_03_H (REG_COMBO_PHY1_P3_BASE + 0x07)
3311 #define REG_COMBO_PHY1_P3_04_L (REG_COMBO_PHY1_P3_BASE + 0x08)
3312 #define REG_COMBO_PHY1_P3_04_H (REG_COMBO_PHY1_P3_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h637 #define REG_COMBO_PHY1_P3_BASE 0x170900UL macro

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