| /utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/mhl/internal/ |
| H A D | halMHL.c | 1050 usClkCount = R2BYTE(REG_COMBO_PHY0_P3_3C_L) & 0x0FFF; in _mhal_mhl_CheckClockStatus()
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/mhl/internal/ |
| H A D | halMHL.c | 1066 usClkCount = R2BYTE(REG_COMBO_PHY0_P3_3C_L) & 0x0FFF; in _mhal_mhl_CheckClockStatus()
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/mhl/internal/ |
| H A D | halMHL.c | 988 usClkCount = R2BYTE(REG_COMBO_PHY0_P3_3C_L) & 0x0FFF; in _mhal_mhl_CheckClockStatus()
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/mhl/internal/ |
| H A D | halMHL.c | 988 usClkCount = R2BYTE(REG_COMBO_PHY0_P3_3C_L) & 0x0FFF; in _mhal_mhl_CheckClockStatus()
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/mhl/internal/ |
| H A D | halMHL.c | 988 usClkCount = R2BYTE(REG_COMBO_PHY0_P3_3C_L) & 0x0FFF; in _mhal_mhl_CheckClockStatus()
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/mhl/internal/ |
| H A D | halMHL.c | 988 usClkCount = R2BYTE(REG_COMBO_PHY0_P3_3C_L) & 0x0FFF; in _mhal_mhl_CheckClockStatus()
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/mhl/internal/ |
| H A D | halMHL.c | 988 usClkCount = R2BYTE(REG_COMBO_PHY0_P3_3C_L) & 0x0FFF; in _mhal_mhl_CheckClockStatus()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/ |
| H A D | mhal_hdmi.c | 815 usClockRate = R2BYTE(REG_COMBO_PHY0_P3_3C_L) * 12 / 128; in _Hal_tmds_GetClockRatePort()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/ |
| H A D | mhal_hdmi.c | 826 usClockRate = R2BYTE(REG_COMBO_PHY0_P3_3C_L) * 12 / 128; in _Hal_tmds_GetClockRatePort()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/ |
| H A D | mhal_hdmi.c | 897 usClockRate = R2BYTE(REG_COMBO_PHY0_P3_3C_L) * 12 / 128; in _Hal_tmds_GetClockRatePort()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/ |
| H A D | mhal_hdmi.c | 826 usClockRate = R2BYTE(REG_COMBO_PHY0_P3_3C_L) * 12 / 128; in _Hal_tmds_GetClockRatePort()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_hdmi.c | 887 usClockRate = R2BYTE(REG_COMBO_PHY0_P3_3C_L) * 12 / 128; in _Hal_tmds_GetClockRatePort()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/ |
| H A D | mhal_hdmi.c | 897 usClockRate = R2BYTE(REG_COMBO_PHY0_P3_3C_L) * 12 / 128; in _Hal_tmds_GetClockRatePort()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/ |
| H A D | mhal_hdmi.c | 818 usClockRate = R2BYTE(REG_COMBO_PHY0_P3_3C_L) * 12 / 128; in _Hal_tmds_GetClockRatePort()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_hdmi.c | 818 usClockRate = R2BYTE(REG_COMBO_PHY0_P3_3C_L) * 12 / 128; in _Hal_tmds_GetClockRatePort()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_hdmi.c | 953 usClockRate = R2BYTE(REG_COMBO_PHY0_P3_3C_L) * 12 / 128; in _Hal_tmds_GetClockRatePort()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/ |
| H A D | mhal_hdmi.c | 818 usClockRate = R2BYTE(REG_COMBO_PHY0_P3_3C_L) * 12 / 128; in _Hal_tmds_GetClockRatePort()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_hdmi.c | 953 usClockRate = R2BYTE(REG_COMBO_PHY0_P3_3C_L) * 12 / 128; in _Hal_tmds_GetClockRatePort()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | hwreg_hdmi.h | 3165 #define REG_COMBO_PHY0_P3_3C_L (REG_COMBO_PHY0_P3_BASE + 0x78) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | hwreg_hdmi.h | 3167 #define REG_COMBO_PHY0_P3_3C_L (REG_COMBO_PHY0_P3_BASE + 0x78) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | hwreg_hdmi.h | 3165 #define REG_COMBO_PHY0_P3_3C_L (REG_COMBO_PHY0_P3_BASE + 0x78) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | hwreg_hdmi.h | 3167 #define REG_COMBO_PHY0_P3_3C_L (REG_COMBO_PHY0_P3_BASE + 0x78) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | hwreg_hdmi.h | 3165 #define REG_COMBO_PHY0_P3_3C_L (REG_COMBO_PHY0_P3_BASE + 0x78) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | hwreg_hdmi.h | 3167 #define REG_COMBO_PHY0_P3_3C_L (REG_COMBO_PHY0_P3_BASE + 0x78) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/ |
| H A D | hwreg_hdmi.h | 3167 #define REG_COMBO_PHY0_P3_3C_L (REG_COMBO_PHY0_P3_BASE + 0x78) macro
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