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Searched refs:REG_COMBO_PHY0_P2_6B_L (Results 1 – 25 of 31) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/mhl/internal/
H A DhalMHL.c469 pMHLSignalStatus->ucImpedanceValue = R2BYTE(REG_COMBO_PHY0_P2_6B_L) >> 12; in _mhal_mhl_HdmiBypassModeSetting()
474 … W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, (pMHLSignalStatus->ucImpedanceValue << 12), BMASK(15:12)); in _mhal_mhl_HdmiBypassModeSetting()
619 pMHLSignalStatus->ucImpedanceValue = R2BYTE(REG_COMBO_PHY0_P2_6B_L) >> 12; in _mhal_mhl_Mhl24bitsModeSetting()
633 W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, usImpedanceSetting, BMASK(15:12)); in _mhal_mhl_Mhl24bitsModeSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/mhl/internal/
H A DhalMHL.c469 pMHLSignalStatus->ucImpedanceValue = R2BYTE(REG_COMBO_PHY0_P2_6B_L) >> 12; in _mhal_mhl_HdmiBypassModeSetting()
474 … W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, (pMHLSignalStatus->ucImpedanceValue << 12), BMASK(15:12)); in _mhal_mhl_HdmiBypassModeSetting()
619 pMHLSignalStatus->ucImpedanceValue = R2BYTE(REG_COMBO_PHY0_P2_6B_L) >> 12; in _mhal_mhl_Mhl24bitsModeSetting()
633 W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, usImpedanceSetting, BMASK(15:12)); in _mhal_mhl_Mhl24bitsModeSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/mhl/internal/
H A DhalMHL.c469 pMHLSignalStatus->ucImpedanceValue = R2BYTE(REG_COMBO_PHY0_P2_6B_L) >> 12; in _mhal_mhl_HdmiBypassModeSetting()
474 … W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, (pMHLSignalStatus->ucImpedanceValue << 12), BMASK(15:12)); in _mhal_mhl_HdmiBypassModeSetting()
619 pMHLSignalStatus->ucImpedanceValue = R2BYTE(REG_COMBO_PHY0_P2_6B_L) >> 12; in _mhal_mhl_Mhl24bitsModeSetting()
633 W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, usImpedanceSetting, BMASK(15:12)); in _mhal_mhl_Mhl24bitsModeSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/mhl/internal/
H A DhalMHL.c469 pMHLSignalStatus->ucImpedanceValue = R2BYTE(REG_COMBO_PHY0_P2_6B_L) >> 12; in _mhal_mhl_HdmiBypassModeSetting()
474 … W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, (pMHLSignalStatus->ucImpedanceValue << 12), BMASK(15:12)); in _mhal_mhl_HdmiBypassModeSetting()
619 pMHLSignalStatus->ucImpedanceValue = R2BYTE(REG_COMBO_PHY0_P2_6B_L) >> 12; in _mhal_mhl_Mhl24bitsModeSetting()
633 W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, usImpedanceSetting, BMASK(15:12)); in _mhal_mhl_Mhl24bitsModeSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/mhl/internal/
H A DhalMHL.c469 pMHLSignalStatus->ucImpedanceValue = R2BYTE(REG_COMBO_PHY0_P2_6B_L) >> 12; in _mhal_mhl_HdmiBypassModeSetting()
474 … W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, (pMHLSignalStatus->ucImpedanceValue << 12), BMASK(15:12)); in _mhal_mhl_HdmiBypassModeSetting()
619 pMHLSignalStatus->ucImpedanceValue = R2BYTE(REG_COMBO_PHY0_P2_6B_L) >> 12; in _mhal_mhl_Mhl24bitsModeSetting()
633 W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, usImpedanceSetting, BMASK(15:12)); in _mhal_mhl_Mhl24bitsModeSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/mhl/internal/
H A DhalMHL.c461 W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, (MHL_IMPEDANCE_VALUE << 12), BMASK(15:12)); in _mhal_mhl_HdmiBypassModeSetting()
570 W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, (ucImpedanceValue << 12), BMASK(15:12)); in _mhal_mhl_Mhl24bitsModeSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/mhl/internal/
H A DhalMHL.c467 W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, (MHL_IMPEDANCE_VALUE << 12), BMASK(15:12)); in _mhal_mhl_HdmiBypassModeSetting()
584 W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, (ucImpedanceValue << 12), BMASK(15:12)); in _mhal_mhl_Mhl24bitsModeSetting()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c721 …W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, bHDMI20Flag? BIT(1): BMASK(2:1), BMASK(2:1)); // [2]: enable clk… in _Hal_tmds_HDMI20PHYSetting()
769 …W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, bYUV420Flag? BMASK(2:1): BIT(1), BMASK(2:1)); // [2]: enable clk… in _Hal_tmds_YUV420PHYSetting()
920 … W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, BMASK(11:8), BMASK(11:8)); // reg_atop_gc_ictrl_pfd_ov in _Hal_tmds_EQBandWidthSetting()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c732 …W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, bHDMI20Flag? BIT(1): BMASK(2:1), BMASK(2:1)); // [2]: enable clk… in _Hal_tmds_HDMI20PHYSetting()
780 …W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, bYUV420Flag? BMASK(2:1): BIT(1), BMASK(2:1)); // [2]: enable clk… in _Hal_tmds_YUV420PHYSetting()
931 … W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, BMASK(11:8), BMASK(11:8)); // reg_atop_gc_ictrl_pfd_ov in _Hal_tmds_EQBandWidthSetting()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c732 …W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, bHDMI20Flag? BIT(1): BMASK(2:1), BMASK(2:1)); // [2]: enable clk… in _Hal_tmds_HDMI20PHYSetting()
780 …W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, bYUV420Flag? BMASK(2:1): BIT(1), BMASK(2:1)); // [2]: enable clk… in _Hal_tmds_YUV420PHYSetting()
931 … W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, BMASK(11:8), BMASK(11:8)); // reg_atop_gc_ictrl_pfd_ov in _Hal_tmds_EQBandWidthSetting()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c793 …W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, bHDMI20Flag? BIT(1): BMASK(2:1), BMASK(2:1)); // [2]: enable clk… in _Hal_tmds_HDMI20PHYSetting()
841 …W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, bYUV420Flag? BMASK(2:1): BIT(1), BMASK(2:1)); // [2]: enable clk… in _Hal_tmds_YUV420PHYSetting()
992 … W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, BMASK(11:8), BMASK(11:8)); // reg_atop_gc_ictrl_pfd_ov in _Hal_tmds_EQBandWidthSetting()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c724 …W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, bHDMI20Flag? BIT(1): BMASK(2:1), BMASK(2:1)); // [2]: enable clk… in _Hal_tmds_HDMI20PHYSetting()
772 …W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, bYUV420Flag? BMASK(2:1): BIT(1), BMASK(2:1)); // [2]: enable clk… in _Hal_tmds_YUV420PHYSetting()
923 … W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, BMASK(11:8), BMASK(11:8)); // reg_atop_gc_ictrl_pfd_ov in _Hal_tmds_EQBandWidthSetting()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c724 …W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, bHDMI20Flag? BIT(1): BMASK(2:1), BMASK(2:1)); // [2]: enable clk… in _Hal_tmds_HDMI20PHYSetting()
772 …W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, bYUV420Flag? BMASK(2:1): BIT(1), BMASK(2:1)); // [2]: enable clk… in _Hal_tmds_YUV420PHYSetting()
923 … W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, BMASK(11:8), BMASK(11:8)); // reg_atop_gc_ictrl_pfd_ov in _Hal_tmds_EQBandWidthSetting()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c859 …W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, bHDMI20Flag? BIT(1): BMASK(2:1), BMASK(2:1)); // [2]: enable clk… in _Hal_tmds_HDMI20PHYSetting()
907 …W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, bYUV420Flag? BMASK(2:1): BIT(1), BMASK(2:1)); // [2]: enable clk… in _Hal_tmds_YUV420PHYSetting()
1058 … W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, BMASK(11:8), BMASK(11:8)); // reg_atop_gc_ictrl_pfd_ov in _Hal_tmds_EQBandWidthSetting()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c724 …W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, bHDMI20Flag? BIT(1): BMASK(2:1), BMASK(2:1)); // [2]: enable clk… in _Hal_tmds_HDMI20PHYSetting()
772 …W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, bYUV420Flag? BMASK(2:1): BIT(1), BMASK(2:1)); // [2]: enable clk… in _Hal_tmds_YUV420PHYSetting()
923 … W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, BMASK(11:8), BMASK(11:8)); // reg_atop_gc_ictrl_pfd_ov in _Hal_tmds_EQBandWidthSetting()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c859 …W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, bHDMI20Flag? BIT(1): BMASK(2:1), BMASK(2:1)); // [2]: enable clk… in _Hal_tmds_HDMI20PHYSetting()
907 …W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, bYUV420Flag? BMASK(2:1): BIT(1), BMASK(2:1)); // [2]: enable clk… in _Hal_tmds_YUV420PHYSetting()
1058 … W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, BMASK(11:8), BMASK(11:8)); // reg_atop_gc_ictrl_pfd_ov in _Hal_tmds_EQBandWidthSetting()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c803 …W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, bHDMI20Flag? BIT(1): BMASK(2:1), BMASK(2:1)); // [2]: enable clk… in _Hal_tmds_HDMI20PHYSetting()
851 …W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, bYUV420Flag? BMASK(2:1): BIT(1), BMASK(2:1)); // [2]: enable clk… in _Hal_tmds_YUV420PHYSetting()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c803 …W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, bHDMI20Flag? BIT(1): BMASK(2:1), BMASK(2:1)); // [2]: enable clk… in _Hal_tmds_HDMI20PHYSetting()
851 …W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, bYUV420Flag? BMASK(2:1): BIT(1), BMASK(2:1)); // [2]: enable clk… in _Hal_tmds_YUV420PHYSetting()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h2743 #define REG_COMBO_PHY0_P2_6B_L (REG_COMBO_PHY0_P2_BASE + 0xD6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h2745 #define REG_COMBO_PHY0_P2_6B_L (REG_COMBO_PHY0_P2_BASE + 0xD6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h2743 #define REG_COMBO_PHY0_P2_6B_L (REG_COMBO_PHY0_P2_BASE + 0xD6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h2745 #define REG_COMBO_PHY0_P2_6B_L (REG_COMBO_PHY0_P2_BASE + 0xD6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h2743 #define REG_COMBO_PHY0_P2_6B_L (REG_COMBO_PHY0_P2_BASE + 0xD6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h2745 #define REG_COMBO_PHY0_P2_6B_L (REG_COMBO_PHY0_P2_BASE + 0xD6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h2745 #define REG_COMBO_PHY0_P2_6B_L (REG_COMBO_PHY0_P2_BASE + 0xD6) macro

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