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Searched refs:REG_COMBO_PHY0_P0_45_L (Results 1 – 25 of 35) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/mhl/internal/
H A DhalMHL.c297 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock t… in _mhal_mhl_HdmiBypassModeSetting()
317 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock t… in _mhal_mhl_HdmiBypassModeSetting()
377 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time v… in _mhal_mhl_Mhl24bitsModeSetting()
397 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time v… in _mhal_mhl_Mhl24bitsModeSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/mhl/internal/
H A DhalMHL.c297 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock t… in _mhal_mhl_HdmiBypassModeSetting()
317 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock t… in _mhal_mhl_HdmiBypassModeSetting()
377 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time v… in _mhal_mhl_Mhl24bitsModeSetting()
397 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time v… in _mhal_mhl_Mhl24bitsModeSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/mhl/internal/
H A DhalMHL.c415 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock t… in _mhal_mhl_HdmiBypassModeSetting()
536 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time v… in _mhal_mhl_Mhl24bitsModeSetting()
1122 W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, 0x6, BMASK(3:0)); in _mhal_mhl_CbusAndClockSelect()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/mhl/internal/
H A DhalMHL.c415 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock t… in _mhal_mhl_HdmiBypassModeSetting()
536 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time v… in _mhal_mhl_Mhl24bitsModeSetting()
1122 W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, 0x6, BMASK(3:0)); in _mhal_mhl_CbusAndClockSelect()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/mhl/internal/
H A DhalMHL.c415 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock t… in _mhal_mhl_HdmiBypassModeSetting()
536 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time v… in _mhal_mhl_Mhl24bitsModeSetting()
1122 W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, 0x6, BMASK(3:0)); in _mhal_mhl_CbusAndClockSelect()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/mhl/internal/
H A DhalMHL.c415 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock t… in _mhal_mhl_HdmiBypassModeSetting()
536 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time v… in _mhal_mhl_Mhl24bitsModeSetting()
1122 W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, 0x6, BMASK(3:0)); in _mhal_mhl_CbusAndClockSelect()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/mhl/internal/
H A DhalMHL.c415 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock t… in _mhal_mhl_HdmiBypassModeSetting()
536 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time v… in _mhal_mhl_Mhl24bitsModeSetting()
1122 W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, 0x6, BMASK(3:0)); in _mhal_mhl_CbusAndClockSelect()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/mhl/internal/
H A DhalMHL.c414 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock t… in _mhal_mhl_HdmiBypassModeSetting()
521 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time v… in _mhal_mhl_Mhl24bitsModeSetting()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_hdmi.c1925 …W2BYTE(REG_COMBO_PHY0_P0_45_L, 0x1F83);// [14:8]: reg_dig_lock_time; [7]: reg_dig_lock_mode; [3:0]… in Hal_HDMI_init()
1980 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, TMDS_DIGITAL_LOCK_CNT_POWER, BMASK(3:0)); // [3:0]: reg_dig_lck_… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/mhl/internal/
H A DhalMHL.c414 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock t… in _mhal_mhl_HdmiBypassModeSetting()
529 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time v… in _mhal_mhl_Mhl24bitsModeSetting()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c4167 …W2BYTE(REG_COMBO_PHY0_P0_45_L + u16bank_offset, 0x1F03);// [14:8]: reg_dig_lock_time; [7]: reg_dig… in Hal_HDMI_init()
4171 …W2BYTE(REG_COMBO_PHY0_P0_45_L + u16bank_offset, 0x1F83);// [14:8]: reg_dig_lock_time; [7]: reg_dig… in Hal_HDMI_init()
4235 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L + u16bank_offset, TMDS_DIGITAL_LOCK_CNT_POWER, BMASK(3:0)); // [3… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_hdmi.c2660 …W2BYTE(REG_COMBO_PHY0_P0_45_L, 0x1F83);// [14:8]: reg_dig_lock_time; [7]: reg_dig_lock_mode; [3:0]… in Hal_HDMI_init()
2714 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, TMDS_DIGITAL_LOCK_CNT_POWER, BMASK(3:0)); // [3:0]: reg_dig_lck_… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c4121 …W2BYTE(REG_COMBO_PHY0_P0_45_L + u16bank_offset, 0x1F83);// [14:8]: reg_dig_lock_time; [7]: reg_dig… in Hal_HDMI_init()
4184 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L + u16bank_offset, TMDS_DIGITAL_LOCK_CNT_POWER, BMASK(3:0)); // [3… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c4230 …W2BYTE(REG_COMBO_PHY0_P0_45_L + u16bank_offset, 0x1F83);// [14:8]: reg_dig_lock_time; [7]: reg_dig… in Hal_HDMI_init()
4293 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L + u16bank_offset, TMDS_DIGITAL_LOCK_CNT_POWER, BMASK(3:0)); // [3… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c4234 …W2BYTE(REG_COMBO_PHY0_P0_45_L + u16bank_offset, 0x1F83);// [14:8]: reg_dig_lock_time; [7]: reg_dig… in Hal_HDMI_init()
4291 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L + u16bank_offset, TMDS_DIGITAL_LOCK_CNT_POWER, BMASK(3:0)); // [3… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c4230 …W2BYTE(REG_COMBO_PHY0_P0_45_L + u16bank_offset, 0x1F83);// [14:8]: reg_dig_lock_time; [7]: reg_dig… in Hal_HDMI_init()
4293 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L + u16bank_offset, TMDS_DIGITAL_LOCK_CNT_POWER, BMASK(3:0)); // [3… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c4234 …W2BYTE(REG_COMBO_PHY0_P0_45_L + u16bank_offset, 0x1F83);// [14:8]: reg_dig_lock_time; [7]: reg_dig… in Hal_HDMI_init()
4291 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L + u16bank_offset, TMDS_DIGITAL_LOCK_CNT_POWER, BMASK(3:0)); // [3… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c4798 …W2BYTE(REG_COMBO_PHY0_P0_45_L + u16bank_offset, 0x1F83);// [14:8]: reg_dig_lock_time; [7]: reg_dig… in Hal_HDMI_init()
4858 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L + u16bank_offset, TMDS_DIGITAL_LOCK_CNT_POWER, BMASK(3:0)); // [3… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c4801 …W2BYTE(REG_COMBO_PHY0_P0_45_L + u16bank_offset, 0x1F83);// [14:8]: reg_dig_lock_time; [7]: reg_dig… in Hal_HDMI_init()
4861 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L + u16bank_offset, TMDS_DIGITAL_LOCK_CNT_POWER, BMASK(3:0)); // [3… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c4356 …W2BYTE(REG_COMBO_PHY0_P0_45_L + u16bank_offset, 0x1F83);// [14:8]: reg_dig_lock_time; [7]: reg_dig… in Hal_HDMI_init()
4419 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L + u16bank_offset, TMDS_DIGITAL_LOCK_CNT_POWER, BMASK(3:0)); // [3… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c4804 …W2BYTE(REG_COMBO_PHY0_P0_45_L + u16bank_offset, 0x1F83);// [14:8]: reg_dig_lock_time; [7]: reg_dig… in Hal_HDMI_init()
4864 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L + u16bank_offset, TMDS_DIGITAL_LOCK_CNT_POWER, BMASK(3:0)); // [3… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c4356 …W2BYTE(REG_COMBO_PHY0_P0_45_L + u16bank_offset, 0x1F83);// [14:8]: reg_dig_lock_time; [7]: reg_dig… in Hal_HDMI_init()
4419 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L + u16bank_offset, TMDS_DIGITAL_LOCK_CNT_POWER, BMASK(3:0)); // [3… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h1635 #define REG_COMBO_PHY0_P0_45_L (REG_COMBO_PHY0_P0_BASE + 0x8A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h1637 #define REG_COMBO_PHY0_P0_45_L (REG_COMBO_PHY0_P0_BASE + 0x8A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h1635 #define REG_COMBO_PHY0_P0_45_L (REG_COMBO_PHY0_P0_BASE + 0x8A) macro

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